It works, but why?
[fpgaboy.git] / System.v
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1
2`timescale 1ns / 1ps
3module ROM(
4 input [15:0] address,
5 inout [7:0] data,
6 input clk,
7 input wr, rd);
8
9 reg [7:0] rom [2047:0];
10 initial $readmemh("rom.hex", rom);
11
12 wire decode = address[15:13] == 0;
13 wire [7:0] odata = rom[address[11:0]];
14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
16endmodule
17
18module InternalRAM(
19 input [15:0] address,
20 inout [7:0] data,
21 input clk,
22 input wr, rd);
23
c87db60a 24 // synthesis attribute ram_style of reg is block
616eebe0 25 reg [7:0] ram [8191:0];
a85b19a7 26
c87db60a 27 wire decode = address[15:13] == 3'b110;
a85b19a7 28 reg [7:0] odata;
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29 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
30
31 always @(negedge clk)
32 begin
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33 if (decode) // This has to go this way. The only way XST knows how to do
34 begin // block ram is chip select, write enable, and always
35 if (wr) // reading. "else if rd" does not cut it ...
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36 ram[address[12:0]] <= data;
37 odata <= ram[address[12:0]];
c87db60a 38 end
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39 end
40endmodule
41
42module Switches(
43 input [15:0] address,
44 inout [7:0] data,
45 input clk,
46 input wr, rd,
47 input [7:0] switches,
9c834ff2 48 output reg [7:0] ledout = 0);
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49
50 wire decode = address == 16'hFF51;
51 reg [7:0] odata;
52 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
53
54 always @(negedge clk)
55 begin
56 if (decode && rd)
57 odata <= switches;
58 else if (decode && wr)
59 ledout <= data;
60 end
61endmodule
62
63module CoreTop(
64 input xtal,
65 input [7:0] switches,
ff7fd7f2 66 input [3:0] buttons,
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67 output wire [7:0] leds,
68 output serio,
69 output wire [3:0] digits,
70 output wire [7:0] seven);
71
06ad3a30 72 wire clk;
a85b19a7 73 CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
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74
75 wire cclk;
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76// IBUFG ibuf (.O(cclk), .I(switches[0] & clk));
77 assign cclk = clk;
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78
79 wire [15:0] addr;
80 wire [7:0] data;
81 wire wr, rd;
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82
83 wire irq, tmrirq;
84 wire [7:0] jaddr;
6c46357c 85 wire [1:0] state;
179b4347 86
a85b19a7 87 GBZ80Core core(
179b4347 88 .clk(clk),
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89 .busaddress(addr),
90 .busdata(data),
91 .buswr(wr),
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92 .busrd(rd),
93 .irq(irq),
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94 .jaddr(jaddr),
95 .state(state));
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96
97 ROM rom(
98 .address(addr),
99 .data(data),
100 .clk(clk),
101 .wr(wr),
102 .rd(rd));
103
104 AddrMon amon(
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105 .addr(addr),
106 .clk(clk),
107 .digit(digits),
108 .out(seven),
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109 .freeze(buttons[0]),
110 .periods(
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111 (state == 2'b00) ? 4'b0010 :
112 (state == 2'b01) ? 4'b0001 :
113 (state == 2'b10) ? 4'b1000 :
114 4'b0100) );
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115
116 Switches sw(
117 .address(addr),
118 .data(data),
119 .clk(clk),
120 .wr(wr),
121 .rd(rd),
122 .ledout(leds),
6c46357c 123 .switches({switches[7:1],1'b0})
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124 );
125
06ad3a30 126 UART nouart ( /* no u */
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127 .clk(clk),
128 .wr(wr),
129 .rd(rd),
130 .addr(addr),
131 .data(data),
132 .serial(serio)
133 );
9aa931d1 134
eb0f2fe1 135 InternalRAM ram(
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136 .address(addr),
137 .data(data),
138 .clk(clk),
139 .wr(wr),
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140 .rd(rd)
141 );
06ad3a30 142
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143 Timer tmr(
144 .clk(clk),
145 .wr(wr),
146 .rd(rd),
147 .addr(addr),
148 .data(data),
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149 .irq(tmrirq)
150 );
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151
152 Interrupt intr(
153 .clk(clk),
154 .rd(rd),
155 .wr(wr),
156 .addr(addr),
157 .data(data),
158 .vblank(0),
159 .lcdc(0),
160 .tovf(tmrirq),
161 .serial(0),
162 .buttons(0),
163 .master(irq),
164 .jaddr(jaddr));
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165endmodule
166
167module TestBench();
62940da0 168 reg clk = 1;
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169 wire [15:0] addr;
170 wire [7:0] data;
171 wire wr, rd;
172
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173 wire irq, tmrirq;
174 wire [7:0] jaddr;
175
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176 wire [7:0] leds;
177 wire [7:0] switches;
a85b19a7 178
179b4347 179 always #62 clk <= ~clk;
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180 GBZ80Core core(
181 .clk(clk),
182 .busaddress(addr),
183 .busdata(data),
184 .buswr(wr),
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185 .busrd(rd),
186 .irq(irq),
187 .jaddr(jaddr));
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188
189 ROM rom(
190 .clk(clk),
191 .address(addr),
192 .data(data),
193 .wr(wr),
194 .rd(rd));
195
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196 InternalRAM ram(
197 .address(addr),
198 .data(data),
199 .clk(clk),
200 .wr(wr),
201 .rd(rd));
a85b19a7 202
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203 wire serio;
204 UART uart(
205 .addr(addr),
206 .data(data),
207 .clk(clk),
208 .wr(wr),
209 .rd(rd),
210 .serial(serio));
a85b19a7 211
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212 Timer tmr(
213 .clk(clk),
214 .wr(wr),
215 .rd(rd),
216 .addr(addr),
217 .data(data),
218 .irq(tmrirq));
219
220 Interrupt intr(
221 .clk(clk),
222 .rd(rd),
223 .wr(wr),
224 .addr(addr),
225 .data(data),
226 .vblank(0),
227 .lcdc(0),
228 .tovf(tmrirq),
229 .serial(0),
230 .buttons(0),
231 .master(irq),
232 .jaddr(jaddr));
233
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234 Switches sw(
235 .clk(clk),
236 .address(addr),
237 .data(data),
238 .wr(wr),
239 .rd(rd),
240 .switches(switches),
241 .ledout(leds));
a85b19a7 242endmodule
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