Merge Memory.

diff --cc Memory.v
index 9c010e71d98e5fe215af482fbe2ce53f45036814,3eb39b3c1224042de62f9cbee87341752cfe2124..4af216d69711924dcc0ccd8fc47f841eb1abed15
--- 1/Memory.v
--- 2/Memory.v
+++ b/Memory.v
@@@ -15,50 -19,29 +15,53 @@@ module Memory
        /* regfile interface */
        output reg [3:0] st_read,
        input [31:0] st_data,
-       input [31:0] base,
-       input [31:0] offset,
 +      
 +      /* stage inputs */
 +      input inbubble,
 +      input [31:0] pc,
 +      input [31:0] insn,
++      input [31:0] op0,
++      input [31:0] op1,
 +      input write_reg,
 +      input [3:0] write_num,
 +      input [31:0] write_data,
  
 -      /* writeback to base */
 -      output reg writeback,
 -      output reg [3:0] regsel,
 -      output reg [31:0] regdata,
 -
 -      /* pc stuff */
 +      /* outputs */
 +      output reg outstall,
 +      output reg outbubble,
        output reg [31:0] outpc,
 -
 -      /* stall */
 -      output outstall,
 -      output reg outbubble
 -);
 +      output reg [31:0] outinsn,
 +      output reg out_write_reg = 1'b0,
 +      output reg [3:0] out_write_num = 4'bxxxx,
 +      output reg [31:0] out_write_data = 32'hxxxxxxxx
 +      );
  
        reg [31:0] addr, raddr, next_regdata;
        reg [3:0] next_regsel;
        reg next_writeback, next_notdone, next_inc_next;
        reg [31:0] align_s1, align_s2, align_rddata;
 +      
 +      wire next_write_reg;
 +      wire [3:0] next_write_num;
 +      wire [31:0] next_write_data;
 +
+       reg [15:0] regs, next_regs;
+ 
        reg notdone = 1'b0;
        reg inc_next = 1'b0;
 -      assign outstall = rw_wait | notdone;
 +
 +      always @(posedge clk)
 +      begin
 +              outpc <= pc;
 +              outinsn <= insn;
 +              outbubble <= rw_wait;
 +              out_write_reg <= next_writeback;
 +              out_write_num <= next_regsel;
 +              out_write_data <= next_regdata;
 +              notdone <= next_notdone;
 +              inc_next <= next_inc_next;
++              regs <= next_regs;
 +      end
  
        always @(*)
        begin
@@@ -79,40 -59,77 +82,81 @@@
                casez(insn)
                `DECODE_LDRSTR_UNDEFINED: begin end
                `DECODE_LDRSTR: begin
 -                      addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
 -                      raddr = insn[24] ? op0 : addr;
 -                      busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
 -                      rd_req = insn[20];
 -                      wr_req = ~insn[20];
 -
 -                      /* rotate to correct position */
 -                      align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
 -                      align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
 -                      /* select byte or word */
 -                      align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
 -
 -                      if(!insn[20]) begin
 -                              st_read = insn[15:12];
 -                              wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
 -                      end
 -                      else if(!inc_next) begin
 -                              next_writeback = 1'b1;
 -                              next_regsel = insn[15:12];
 -                              next_regdata = align_rddata;
 -                              next_inc_next = 1'b1;
 -                      end
 -                      else if(insn[21]) begin
 -                              next_writeback = 1'b1;
 -                              next_regsel = insn[19:16];
 -                              next_regdata = addr;
 +                      if (!inbubble) begin
 +                              outstall = rw_wait | notdone;
 +                      
-                               addr = insn[23] ? base + offset : base - offset; /* up/down select */
-                               raddr = insn[24] ? base : addr;
-                               busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
++                              addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
++                              raddr = insn[24] ? op0 : addr; /* pre/post increment */
++                              busaddr = {raddr[31:2], 2'b0};
 +                              rd_req = insn[20];
 +                              wr_req = ~insn[20];
 +                              
 +                              /* rotate to correct position */
 +                              align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
 +                              align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
 +                              /* select byte or word */
 +                              align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
 +                              
 +                              if(!insn[20]) begin
 +                                      st_read = insn[15:12];
 +                                      wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
 +                              end
 +                              else if(!inc_next) begin
 +                                      next_write_reg = 1'b1;
 +                                      next_write_num = insn[15:12];
 +                                      next_write_data = align_rddata;
 +                                      next_inc_next = 1'b1;
 +                              end
 +                              else if(insn[21]) begin
 +                                      next_write_reg = 1'b1;
 +                                      next_write_num = insn[19:16];
 +                                      next_write_data = addr;
 +                              end
 +                              next_notdone = rw_wait & insn[20] & insn[21];
                        end
 -                      next_notdone = rw_wait & insn[20] & insn[21];
                end
                `DECODE_LDMSTM: begin
+                       busaddr = {op0[31:2], 2'b0};
+                       rd_req = insn[20];
+                       wr_req = ~insn[20];
+                       casez(regs)
+                       16'b???????????????1: begin
+                               next_regs = regs;
+                       end
+                       16'b??????????????10: begin
+                       end
+                       16'b?????????????100: begin
+                       end
+                       16'b????????????1000: begin
+                       end
+                       16'b???????????10000: begin
+                       end
+                       16'b??????????100000: begin
+                       end
+                       16'b?????????1000000: begin
+                       end
+                       16'b????????10000000: begin
+                       end
+                       16'b???????100000000: begin
+                       end
+                       16'b??????1000000000: begin
+                       end
+                       16'b?????10000000000: begin
+                       end
+                       16'b????100000000000: begin
+                       end
+                       16'b???1000000000000: begin
+                       end
+                       16'b??10000000000000: begin
+                       end
+                       16'b?100000000000000: begin
+                       end
+                       16'b1000000000000000: begin
+                       end
+                       default: begin
+                               next_inc_next = 1'b1;
+                       end
+                       endcase
                end
                default: begin end
                endcase