Merge Memory.

diff --git a/Memory.v b/Memory.v
index 9c010e71d98e5fe215af482fbe2ce53f45036814..4af216d69711924dcc0ccd8fc47f841eb1abed15 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -20,8 +20,8 @@ module Memory(
        input inbubble,
        input [31:0] pc,
        input [31:0] insn,
-       input [31:0] base,
-       input [31:0] offset,
+       input [31:0] op0,
+       input [31:0] op1,
        input write_reg,
        input [3:0] write_num,
        input [31:0] write_data,
@@ -45,6 +45,8 @@ module Memory(
        wire [3:0] next_write_num;
        wire [31:0] next_write_data;
 
+       reg [15:0] regs, next_regs;
+
        reg notdone = 1'b0;
        reg inc_next = 1'b0;
 
@@ -58,6 +60,7 @@ module Memory(
                out_write_data <= next_regdata;
                notdone <= next_notdone;
                inc_next <= next_inc_next;
+               regs <= next_regs;
        end
 
        always @(*)
@@ -82,9 +85,9 @@ module Memory(
                        if (!inbubble) begin
                                outstall = rw_wait | notdone;
                        
-                               addr = insn[23] ? base + offset : base - offset; /* up/down select */
-                               raddr = insn[24] ? base : addr;
-                               busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
+                               addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+                               raddr = insn[24] ? op0 : addr; /* pre/post increment */
+                               busaddr = {raddr[31:2], 2'b0};
                                rd_req = insn[20];
                                wr_req = ~insn[20];
                                
@@ -113,6 +116,47 @@ module Memory(
                        end
                end
                `DECODE_LDMSTM: begin
+                       busaddr = {op0[31:2], 2'b0};
+                       rd_req = insn[20];
+                       wr_req = ~insn[20];
+                       casez(regs)
+                       16'b???????????????1: begin
+                               next_regs = regs;
+                       end
+                       16'b??????????????10: begin
+                       end
+                       16'b?????????????100: begin
+                       end
+                       16'b????????????1000: begin
+                       end
+                       16'b???????????10000: begin
+                       end
+                       16'b??????????100000: begin
+                       end
+                       16'b?????????1000000: begin
+                       end
+                       16'b????????10000000: begin
+                       end
+                       16'b???????100000000: begin
+                       end
+                       16'b??????1000000000: begin
+                       end
+                       16'b?????10000000000: begin
+                       end
+                       16'b????100000000000: begin
+                       end
+                       16'b???1000000000000: begin
+                       end
+                       16'b??10000000000000: begin
+                       end
+                       16'b?100000000000000: begin
+                       end
+                       16'b1000000000000000: begin
+                       end
+                       default: begin
+                               next_inc_next = 1'b1;
+                       end
+                       endcase
                end
                default: begin end
                endcase