Merge Memory.
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Tue, 6 Jan 2009 07:31:00 +0000 (02:31 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Tue, 6 Jan 2009 07:31:00 +0000 (02:31 -0500)
Memory.v
system.v

index 3eb39b3..4af216d 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -3,10 +3,6 @@
 module Memory(
        input clk,
        input Nrst,
-       input [31:0] pc,
-       input [31:0] insn,
-       input [31:0] op0,
-       input [31:0] op1,
 
        /* bus interface */
        output reg [31:0] busaddr,
@@ -19,29 +15,53 @@ module Memory(
        /* regfile interface */
        output reg [3:0] st_read,
        input [31:0] st_data,
+       
+       /* stage inputs */
+       input inbubble,
+       input [31:0] pc,
+       input [31:0] insn,
+       input [31:0] op0,
+       input [31:0] op1,
+       input write_reg,
+       input [3:0] write_num,
+       input [31:0] write_data,
 
-       /* writeback to base */
-       output reg writeback,
-       output reg [3:0] regsel,
-       output reg [31:0] regdata,
-
-       /* pc stuff */
+       /* outputs */
+       output reg outstall,
+       output reg outbubble,
        output reg [31:0] outpc,
-
-       /* stall */
-       output outstall,
-       output reg outbubble
-);
+       output reg [31:0] outinsn,
+       output reg out_write_reg = 1'b0,
+       output reg [3:0] out_write_num = 4'bxxxx,
+       output reg [31:0] out_write_data = 32'hxxxxxxxx
+       );
 
        reg [31:0] addr, raddr, next_regdata;
        reg [3:0] next_regsel;
        reg next_writeback, next_notdone, next_inc_next;
        reg [31:0] align_s1, align_s2, align_rddata;
+       
+       wire next_write_reg;
+       wire [3:0] next_write_num;
+       wire [31:0] next_write_data;
+
        reg [15:0] regs, next_regs;
 
        reg notdone = 1'b0;
        reg inc_next = 1'b0;
-       assign outstall = rw_wait | notdone;
+
+       always @(posedge clk)
+       begin
+               outpc <= pc;
+               outinsn <= insn;
+               outbubble <= rw_wait;
+               out_write_reg <= next_writeback;
+               out_write_num <= next_regsel;
+               out_write_data <= next_regdata;
+               notdone <= next_notdone;
+               inc_next <= next_inc_next;
+               regs <= next_regs;
+       end
 
        always @(*)
        begin
@@ -53,40 +73,47 @@ module Memory(
                busaddr = 32'hxxxxxxxx;
                outstall = 1'b0;
                next_notdone = 1'b0;
-               next_regsel = 4'hx;
-               next_regdata = 32'hxxxxxxxx;
+               next_write_reg = write_reg;
+               next_write_num = write_num;
+               next_write_data = write_data;
                next_inc_next = 1'b0;
+               outstall = 1'b0;
+               
                casez(insn)
                `DECODE_LDRSTR_UNDEFINED: begin end
                `DECODE_LDRSTR: begin
-                       addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
-                       raddr = insn[24] ? op0 : addr;
-                       busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
-                       rd_req = insn[20];
-                       wr_req = ~insn[20];
-
-                       /* rotate to correct position */
-                       align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
-                       align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
-                       /* select byte or word */
-                       align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
-
-                       if(!insn[20]) begin
-                               st_read = insn[15:12];
-                               wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
-                       end
-                       else if(!inc_next) begin
-                               next_writeback = 1'b1;
-                               next_regsel = insn[15:12];
-                               next_regdata = align_rddata;
-                               next_inc_next = 1'b1;
-                       end
-                       else if(insn[21]) begin
-                               next_writeback = 1'b1;
-                               next_regsel = insn[19:16];
-                               next_regdata = addr;
+                       if (!inbubble) begin
+                               outstall = rw_wait | notdone;
+                       
+                               addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+                               raddr = insn[24] ? op0 : addr; /* pre/post increment */
+                               busaddr = {raddr[31:2], 2'b0};
+                               rd_req = insn[20];
+                               wr_req = ~insn[20];
+                               
+                               /* rotate to correct position */
+                               align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+                               align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+                               /* select byte or word */
+                               align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+                               
+                               if(!insn[20]) begin
+                                       st_read = insn[15:12];
+                                       wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
+                               end
+                               else if(!inc_next) begin
+                                       next_write_reg = 1'b1;
+                                       next_write_num = insn[15:12];
+                                       next_write_data = align_rddata;
+                                       next_inc_next = 1'b1;
+                               end
+                               else if(insn[21]) begin
+                                       next_write_reg = 1'b1;
+                                       next_write_num = insn[19:16];
+                                       next_write_data = addr;
+                               end
+                               next_notdone = rw_wait & insn[20] & insn[21];
                        end
-                       next_notdone = rw_wait & insn[20] & insn[21];
                end
                `DECODE_LDMSTM: begin
                        busaddr = {op0[31:2], 2'b0};
@@ -134,18 +161,4 @@ module Memory(
                default: begin end
                endcase
        end
-
-
-       always @(posedge clk)
-       begin
-               outpc <= pc;
-               outbubble <= rw_wait;
-               writeback <= next_writeback;
-               regsel <= next_regsel;
-               regdata <= next_regdata;
-               notdone <= next_notdone;
-               inc_next <= next_inc_next;
-               regs <= next_regs;
-       end
-
 endmodule
index 6fd0b8b..da9d701 100644 (file)
--- a/system.v
+++ b/system.v
@@ -1,4 +1,5 @@
 `define BUS_ICACHE 0
+`define BUS_DCACHE 1
 
 module System(input clk);
        wire [7:0] bus_req;
@@ -9,23 +10,30 @@ module System(input clk);
        wire bus_rd, bus_wr;
        wire bus_ready;
 
-       wire bus_req_icache;    
-       assign bus_req = {7'b0, bus_req_icache};
+       wire bus_req_icache;
+       wire bus_req_dcache;
+       assign bus_req = {6'b0, bus_req_dcache, bus_req_icache};
        wire bus_ack_icache = bus_ack[`BUS_ICACHE];
+       wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
        
        wire [31:0] bus_addr_icache;
        wire [31:0] bus_wdata_icache;
        wire bus_rd_icache;
        wire bus_wr_icache;
        
+       wire [31:0] bus_addr_dcache;
+       wire [31:0] bus_wdata_dcache;
+       wire bus_rd_dcache;
+       wire bus_wr_dcache;
+       
        wire [31:0] bus_rdata_blockram;
        wire bus_ready_blockram;
        
-       assign bus_addr = bus_addr_icache;
+       assign bus_addr = bus_addr_icache | bus_addr_dcache;
        assign bus_rdata = bus_rdata_blockram;
-       assign bus_wdata = bus_wdata_icache;
-       assign bus_rd = bus_rd_icache;
-       assign bus_wr = bus_wr_icache;
+       assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
+       assign bus_rd = bus_rd_icache | bus_rd_dcache;
+       assign bus_wr = bus_wr_icache | bus_wr_dcache;
        assign bus_ready = bus_ready_blockram;
 
        wire [31:0] icache_rd_addr;
@@ -33,6 +41,11 @@ module System(input clk);
        wire icache_rd_wait;
        wire [31:0] icache_rd_data;
        
+       wire [31:0] dcache_addr;
+       wire dcache_rd_req, dcache_wr_req;
+       wire dcache_rw_wait;
+       wire [31:0] dcache_wr_data, dcache_rd_data;
+       
        wire stall_cause_issue;
        wire stall_cause_execute;
        
@@ -70,6 +83,15 @@ module System(input clk);
                .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
                .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
        
+       DCache dcache(
+               .clk(clk),
+               .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
+               .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
+               .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
+               .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
+               .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
+               .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
+
        BlockRAM blockram(
                .clk(clk),
                .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
@@ -118,7 +140,7 @@ module System(input clk);
                .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
                .write_data(execute_out_write_data),
                .jmp(jmp), .jmppc(jmppc),
-               .outpc(pc_out_execute), .insn(insn_out_execute));
+               .outpc(pc_out_execute), .outinsn(insn_out_execute));
        assign execute_out_backflush = jmp;
 
        reg [31:0] clockno = 0;
This page took 0.055277 seconds and 4 git commands to generate.