Global: More re-piping, and a bugfix for a bug recently introduced. (Regressions...

diff --git a/Decode.v b/Decode.v
index 7accb9d4c130735f2b99ea5277248eab6f508738..a989f42d91dbf2beeb361155c73d684716073523 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -5,14 +5,14 @@ module Decode(
        input stall,
        input [31:0] insn_1a,
        input [31:0] pc_1a,
        input stall,
        input [31:0] insn_1a,
        input [31:0] pc_1a,

-       input [31:0] incpsr,
-       input [31:0] inspsr,
-       output reg [31:0] op0,
-       output reg [31:0] op1,
-       output reg [31:0] op2,
-       output reg carry,
-       output reg [31:0] outcpsr,
-       output reg [31:0] outspsr,
+       input [31:0] cpsr_1a,
+       input [31:0] spsr_1a,
+       output reg [31:0] op0_2a,
+       output reg [31:0] op1_2a,
+       output reg [31:0] op2_2a,
+       output reg carry_2a,
+       output reg [31:0] cpsr_2a,
+       output reg [31:0] spsr_2a,

 
        output reg [3:0] rf__read_0_1a,
        output reg [3:0] rf__read_1_1a,
 
        output reg [3:0] rf__read_0_1a,
        output reg [3:0] rf__read_1_1a,


@@ -24,8 +24,8 @@ module Decode(
 
        wire [31:0] regs0, regs1, regs2;
        reg [31:0] rpc;
 
        wire [31:0] regs0, regs1, regs2;
        reg [31:0] rpc;

-       reg [31:0] op0_out, op1_out, op2_out;
-       reg carry_out;
+       reg [31:0] op0_1a, op1_1a, op2_1a;
+       reg carry_1a;

 
        /* shifter stuff */
        wire [31:0] shift_oper;
 
        /* shifter stuff */
        wire [31:0] shift_oper;


@@ -40,7 +40,7 @@ module Decode(
        IREALLYHATEARMSHIFT shift(.insn(insn_1a),
                                  .operand(regs1),
                                  .reg_amt(regs2),
        IREALLYHATEARMSHIFT shift(.insn(insn_1a),
                                  .operand(regs1),
                                  .reg_amt(regs2),

-                                 .cflag_in(incpsr[`CPSR_C]),
+                                 .cflag_in(cpsr_1a[`CPSR_C]),

                                  .res(shift_res),
                                  .cflag_out(shift_cflag_out));
 
                                  .res(shift_res),
                                  .cflag_out(shift_cflag_out));
 


@@ -143,86 +143,86 @@ module Decode(
        end
        
        always @(*) begin
        end
        
        always @(*) begin

-               op0_out = 32'hxxxxxxxx;
-               op1_out = 32'hxxxxxxxx;
-               op2_out = 32'hxxxxxxxx;
-               carry_out = 1'bx;
+               op0_1a = 32'hxxxxxxxx;
+               op1_1a = 32'hxxxxxxxx;
+               op2_1a = 32'hxxxxxxxx;
+               carry_1a = 1'bx;

                
                casez (insn_1a)
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin
                
                casez (insn_1a)
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin

-                       op0_out = regs0;
-                       op1_out = regs1;
-                       op2_out = regs2;
+                       op0_1a = regs0;
+                       op1_1a = regs1;
+                       op2_1a = regs2;

                end
                `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
                begin end
                `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */
                end
                `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
                begin end
                `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */

-                       op0_out = regs0;
+                       op0_1a = regs0;

                `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
                        if(insn_1a[25]) begin     /* the constant case */
                `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
                        if(insn_1a[25]) begin     /* the constant case */

-                               op0_out = rotate_res;
+                               op0_1a = rotate_res;

                        end else begin
                        end else begin

-                               op0_out = regs0;
+                               op0_1a = regs0;

                        end
                `DECODE_ALU_SWP:        /* Atomic swap */
                begin
                        end
                `DECODE_ALU_SWP:        /* Atomic swap */
                begin

-                       op0_out = regs0;
-                       op1_out = regs1;
+                       op0_1a = regs0;
+                       op1_1a = regs1;

                end
                `DECODE_ALU_BX:         /* Branch and exchange */
                end
                `DECODE_ALU_BX:         /* Branch and exchange */

-                       op0_out = regs0;
+                       op0_1a = regs0;

                `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
                begin
                `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
                begin

-                       op0_out = regs0;
-                       op1_out = regs1;
-                       op2_out = regs2;
+                       op0_1a = regs0;
+                       op1_1a = regs1;
+                       op2_1a = regs2;

                end
                `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
                begin
                end
                `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
                begin

-                       op0_out = regs0;
-                       op1_out = {24'b0, insn_1a[11:8], insn_1a[3:0]};
-                       op2_out = regs1;
+                       op0_1a = regs0;
+                       op1_1a = {24'b0, insn_1a[11:8], insn_1a[3:0]};
+                       op2_1a = regs1;

                end
                `DECODE_ALU:            /* ALU */
                begin
                end
                `DECODE_ALU:            /* ALU */
                begin

-                       op0_out = regs0;
+                       op0_1a = regs0;

                        if(insn_1a[25]) begin     /* the constant case */
                        if(insn_1a[25]) begin     /* the constant case */

-                               carry_out = incpsr[`CPSR_C];
-                               op1_out = rotate_res;
+                               carry_1a = cpsr_1a[`CPSR_C];
+                               op1_1a = rotate_res;

                        end else begin
                        end else begin

-                               carry_out = shift_cflag_out;
-                               op1_out = shift_res;
+                               carry_1a = shift_cflag_out;
+                               op1_1a = shift_res;

                        end
                end
                `DECODE_LDRSTR:         /* Single data transfer */
                begin
                        end
                end
                `DECODE_LDRSTR:         /* Single data transfer */
                begin

-                       op0_out = regs0;
+                       op0_1a = regs0;

                        if(!insn_1a[25] /* immediate */) begin
                        if(!insn_1a[25] /* immediate */) begin

-                               op1_out = {20'b0, insn_1a[11:0]};
-                               carry_out = incpsr[`CPSR_C];
+                               op1_1a = {20'b0, insn_1a[11:0]};
+                               carry_1a = cpsr_1a[`CPSR_C];

                        end else begin
                        end else begin

-                               op1_out = shift_res;
-                               carry_out = shift_cflag_out;
+                               op1_1a = shift_res;
+                               carry_1a = shift_cflag_out;

                        end
                        end

-                       op2_out = regs2;
+                       op2_1a = regs2;

                end
                `DECODE_LDMSTM:         /* Block data transfer */
                begin
                end
                `DECODE_LDMSTM:         /* Block data transfer */
                begin

-                       op0_out = regs0;
-                       op1_out = {16'b0, insn_1a[15:0]};
+                       op0_1a = regs0;
+                       op1_1a = {16'b0, insn_1a[15:0]};

                end
                `DECODE_BRANCH:         /* Branch */
                end
                `DECODE_BRANCH:         /* Branch */

-                       op0_out = {{6{insn_1a[23]}}, insn_1a[23:0], 2'b0};
+                       op0_1a = {{6{insn_1a[23]}}, insn_1a[23:0], 2'b0};

                `DECODE_LDCSTC:         /* Coprocessor data transfer */
                begin
                `DECODE_LDCSTC:         /* Coprocessor data transfer */
                begin

-                       op0_out = regs0;
-                       op1_out = {24'b0, insn_1a[7:0]};
+                       op0_1a = regs0;
+                       op1_1a = {24'b0, insn_1a[7:0]};

                end
                `DECODE_CDP:            /* Coprocessor data op */
                begin end
                `DECODE_MRCMCR:         /* Coprocessor register transfer */
                end
                `DECODE_CDP:            /* Coprocessor data op */
                begin end
                `DECODE_MRCMCR:         /* Coprocessor register transfer */

-                       op0_out = regs0;
+                       op0_1a = regs0;

                `DECODE_SWI:            /* SWI */
                begin end
                endcase
                `DECODE_SWI:            /* SWI */
                begin end
                endcase


@@ -231,12 +231,12 @@ module Decode(
        always @ (posedge clk) begin
                if (!stall)
                begin
        always @ (posedge clk) begin
                if (!stall)
                begin

-                       op0 <= op0_out;   /* Rn - always */
-                       op1 <= op1_out; /* 'operand 2' - Rm */
-                       op2 <= op2_out;   /* thirdedge - Rs */
-                       carry <= carry_out;
-                       outcpsr <= incpsr;
-                       outspsr <= inspsr;
+                       op0_2a <= op0_1a;   /* Rn - always */
+                       op1_2a <= op1_1a; /* 'operand 2' - Rm */
+                       op2_2a <= op2_1a;   /* thirdedge - Rs */
+                       carry_2a <= carry_1a;
+                       cpsr_2a <= cpsr_1a;
+                       spsr_2a <= spsr_1a;

                end
        end
 
                end
        end
 

diff --git a/Execute.v b/Execute.v
index c1049ba1f0edbc6bc074445f1b1cac67a188edae..71f12e951be04cac1a78b85cdcf06b869446e6a1 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -2,32 +2,32 @@ module Execute(
        input clk,
        input Nrst,     /* XXX not used yet */
        
        input clk,
        input Nrst,     /* XXX not used yet */
        

-       input stall,
+       input stall_2a,

        input flush,
        
        input flush,
        

-       input inbubble,
-       input [31:0] pc,
-       input [31:0] insn,
-       input [31:0] cpsr,
-       input [31:0] spsr,
-       input [31:0] op0,
-       input [31:0] op1,
-       input [31:0] op2,
-       input carry,
+       input bubble_2a,
+       input [31:0] pc_2a,
+       input [31:0] insn_2a,
+       input [31:0] cpsr_2a,
+       input [31:0] spsr_2a,
+       input [31:0] op0_2a,
+       input [31:0] op1_2a,
+       input [31:0] op2_2a,
+       input carry_2a,

        
        

-       output reg outstall = 0,
-       output reg outbubble = 1,
+       output reg outstall_2a = 0,
+       output reg bubble_3a = 1,

        output reg [31:0] outcpsr = 0,
        output reg [31:0] outspsr = 0,
        output reg outcpsrup = 0,
        output reg [31:0] outcpsr = 0,
        output reg [31:0] outspsr = 0,
        output reg outcpsrup = 0,

-       output reg write_reg = 1'bx,
-       output reg [3:0] write_num = 4'bxxxx,
-       output reg [31:0] write_data = 32'hxxxxxxxx,
-       output reg [31:0] jmppc,
-       output reg jmp,
-       output reg [31:0] outpc,
-       output reg [31:0] outinsn,
-       output reg [31:0] outop0, outop1, outop2
+       output reg write_reg_3a = 1'bx,
+       output reg [3:0] write_num_3a = 4'bxxxx,
+       output reg [31:0] write_data_3a = 32'hxxxxxxxx,
+       output reg [31:0] jmppc_2a,
+       output reg jmp_2a,
+       output reg [31:0] pc_3a,
+       output reg [31:0] insn_3a,
+       output reg [31:0] op0_3a, op1_3a, op2_3a

        );
        
        reg mult_start;
        );
        
        reg mult_start;


@@ -35,19 +35,19 @@ module Execute(
        wire mult_done;
        wire [31:0] mult_result;
        
        wire mult_done;
        wire [31:0] mult_result;
        

-       reg [31:0] alu_in0, alu_in1;
-       reg [3:0] alu_op;
-       reg alu_setflags;
-       wire [31:0] alu_result, alu_outcpsr;
-       wire alu_setres;
+       reg [31:0] alu_in0_2a, alu_in1_2a;
+       reg [3:0] alu_op_2a;
+       reg alu_setflags_2a;
+       wire [31:0] alu_result_2a, alu_outcpsr_2a;
+       wire alu_setres_2a;

        
        

-       reg next_outbubble;
+       reg next_bubble_3a;

        reg [31:0] next_outcpsr, next_outspsr;
        reg next_outcpsrup;
        reg [31:0] next_outcpsr, next_outspsr;
        reg next_outcpsrup;

-       reg next_write_reg;
-       reg [3:0] next_write_num;
-
-       reg [31:0] next_write_data;
+       
+       reg next_write_reg_3a;
+       reg [3:0] next_write_num_3a;
+       reg [31:0] next_write_data_3a;

 
        Multiplier multiplier(
                .clk(clk), .Nrst(Nrst),
 
        Multiplier multiplier(
                .clk(clk), .Nrst(Nrst),


@@ -56,101 +56,101 @@ module Execute(
        
        ALU alu(
                .clk(clk), .Nrst(Nrst),
        
        ALU alu(
                .clk(clk), .Nrst(Nrst),

-               .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
-               .setflags(alu_setflags), .shifter_carry(carry),
-               .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
+               .in0(alu_in0_2a), .in1(alu_in1_2a), .cpsr(cpsr_2a), .op(alu_op_2a),
+               .setflags(alu_setflags_2a), .shifter_carry(carry_2a),
+               .result(alu_result_2a), .cpsr_out(alu_outcpsr_2a), .setres(alu_setres_2a));

 
        always @(posedge clk)
        begin
 
        always @(posedge clk)
        begin

-               if (!stall)
+               if (!stall_2a)

                begin
                begin

-                       outbubble <= next_outbubble;
+                       bubble_3a <= next_bubble_3a;

                        outcpsr <= next_outcpsr;
                        outspsr <= next_outspsr;
                        outcpsrup <= next_outcpsrup;
                        outcpsr <= next_outcpsr;
                        outspsr <= next_outspsr;
                        outcpsrup <= next_outcpsrup;

-                       write_reg <= next_write_reg;
-                       write_num <= next_write_num;
-                       write_data <= next_write_data;
-                       outpc <= pc;
-                       outinsn <= insn;
-                       outop0 <= op0;
-                       outop1 <= op1;
-                       outop2 <= op2;
+                       write_reg_3a <= next_write_reg_3a;
+                       write_num_3a <= next_write_num_3a;
+                       write_data_3a <= next_write_data_3a;
+                       pc_3a <= pc_2a;
+                       insn_3a <= insn_2a;
+                       op0_3a <= op0_2a;
+                       op1_3a <= op1_2a;
+                       op2_3a <= op2_2a;

                end
        end
        
        reg delayedflush = 0;
        always @(posedge clk)
                end
        end
        
        reg delayedflush = 0;
        always @(posedge clk)

-               if (flush && outstall /* halp! I can't do it now, maybe later? */)
+               if (flush && outstall_2a /* halp! I can't do it now, maybe later? */)

                        delayedflush <= 1;
                        delayedflush <= 1;

-               else if (!outstall /* anything has been handled this time around */)
+               else if (!outstall_2a /* anything has been handled this time around */)

                        delayedflush <= 0;
 
                        delayedflush <= 0;
 

-       reg prevstall = 0;
+       reg outstall_3a = 0;

        always @(posedge clk)
        always @(posedge clk)

-               prevstall <= outstall;
+               outstall_3a <= outstall_2a;

        
        always @(*)
        begin
        
        always @(*)
        begin

-               outstall = stall;
+               outstall_2a = stall_2a;

                
                

-               casez (insn)
+               casez (insn_2a)

                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */

-                       outstall = outstall | ((!prevstall | !mult_done) && !inbubble);
+                       outstall_2a = outstall_2a | ((!outstall_3a | !mult_done) && !bubble_2a);

                endcase
        end
        
        /* ALU inputs */
        always @(*)
        begin
                endcase
        end
        
        /* ALU inputs */
        always @(*)
        begin

-               alu_in0 = op0;
-               alu_in1 = op1;
-               alu_op = insn[24:21];
-               alu_setflags = insn[20] /* S */;
+               alu_in0_2a = op0_2a;
+               alu_in1_2a = op1_2a;
+               alu_op_2a = insn_2a[24:21];
+               alu_setflags_2a = insn_2a[20] /* S */;

        end
        
        /* Register outputs */
        always @(*)
        begin
        end
        
        /* Register outputs */
        always @(*)
        begin

-               next_outcpsr = cpsr;
-               next_outspsr = spsr;
+               next_outcpsr = cpsr_2a;
+               next_outspsr = spsr_2a;

                next_outcpsrup = 0;
                next_outcpsrup = 0;

-               next_write_reg = 0;
-               next_write_num = 4'hx;
-               next_write_data = 32'hxxxxxxxx;
+               next_write_reg_3a = 0;
+               next_write_num_3a = 4'hx;
+               next_write_data_3a = 32'hxxxxxxxx;

                
                

-               casez(insn)
+               casez(insn_2a)

                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin

-                       next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
-                       next_outcpsrup = insn[20] /* S */;
-                       next_write_reg = 1;
-                       next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
-                       next_write_data = mult_result;
+                       next_outcpsr = insn_2a[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr_2a[28] /* V */, cpsr_2a[27:0]} : cpsr_2a;
+                       next_outcpsrup = insn_2a[20] /* S */;
+                       next_write_reg_3a = 1;
+                       next_write_num_3a = insn_2a[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
+                       next_write_data_3a = mult_result;

                end
                `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
                begin
                end
                `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
                begin

-                       next_write_reg = 1;
-                       next_write_num = insn[15:12];
-                       if (insn[22] /* Ps */)
-                               next_write_data = spsr;
+                       next_write_reg_3a = 1;
+                       next_write_num_3a = insn_2a[15:12];
+                       if (insn_2a[22] /* Ps */)
+                               next_write_data_3a = spsr_2a;

                        else
                        else

-                               next_write_data = cpsr;
+                               next_write_data_3a = cpsr_2a;

                end
                `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
                `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
                begin
                end
                `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
                `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
                begin

-                       if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))       /* flags only */
+                       if ((cpsr_2a[4:0] == `MODE_USR) || (insn_2a[16] /* that random bit */ == 1'b0)) /* flags only */

                        begin
                        begin

-                               if (insn[22] /* Ps */)
-                                       next_outspsr = {op0[31:29], spsr[28:0]};
+                               if (insn_2a[22] /* Ps */)
+                                       next_outspsr = {op0_2a[31:29], spsr_2a[28:0]};

                                else
                                else

-                                       next_outcpsr = {op0[31:29], cpsr[28:0]};
+                                       next_outcpsr = {op0_2a[31:29], cpsr_2a[28:0]};

                        end else begin
                        end else begin

-                               if (insn[22] /* Ps */)
-                                       next_outspsr = op0;
+                               if (insn_2a[22] /* Ps */)
+                                       next_outspsr = op0_2a;

                                else
                                else

-                                       next_outcpsr = op0;
+                                       next_outcpsr = op0_2a;

                        end
                        next_outcpsrup = 1;
                end
                        end
                        next_outcpsrup = 1;
                end


@@ -161,15 +161,15 @@ module Execute(
                begin end
                `DECODE_ALU:            /* ALU */
                begin
                begin end
                `DECODE_ALU:            /* ALU */
                begin

-                       if (alu_setres) begin
-                               next_write_reg = 1;
-                               next_write_num = insn[15:12] /* Rd */;
-                               next_write_data = alu_result;
+                       if (alu_setres_2a) begin
+                               next_write_reg_3a = 1;
+                               next_write_num_3a = insn_2a[15:12] /* Rd */;
+                               next_write_data_3a = alu_result_2a;

                        end
                        
                        end
                        

-                       if (insn[20] /* S */) begin
+                       if (insn_2a[20] /* S */) begin

                                next_outcpsrup = 1;
                                next_outcpsrup = 1;

-                               next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
+                               next_outcpsr = ((insn_2a[15:12] == 4'b1111) && insn_2a[20]) ? spsr_2a : alu_outcpsr_2a;

                        end
                end
                `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
                        end
                end
                `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */


@@ -178,10 +178,10 @@ module Execute(
                begin end
                `DECODE_BRANCH:         /* Branch */
                begin
                begin end
                `DECODE_BRANCH:         /* Branch */
                begin

-                       if(insn[24] /* L */) begin
-                               next_write_reg = 1;
-                               next_write_num = 4'hE; /* link register */
-                               next_write_data = pc + 32'h4;
+                       if(insn_2a[24] /* L */) begin
+                               next_write_reg_3a = 1;
+                               next_write_num_3a = 4'hE; /* link register */
+                               next_write_data_3a = pc_2a + 32'h4;

                        end
                end
                endcase
                        end
                end
                endcase


@@ -195,15 +195,15 @@ module Execute(
                mult_in0 = 32'hxxxxxxxx;
                mult_in1 = 32'hxxxxxxxx;
                
                mult_in0 = 32'hxxxxxxxx;
                mult_in1 = 32'hxxxxxxxx;
                

-               casez(insn)
+               casez(insn_2a)

                `DECODE_ALU_MULT:
                begin
                `DECODE_ALU_MULT:
                begin

-                       if (!prevstall /* i.e., this is a new one */ && !inbubble /* i.e., this is a real one */)
+                       if (!outstall_3a /* i.e., this is a new one */ && !bubble_2a /* i.e., this is a real one */)

                        begin
                                mult_start = 1;
                        begin
                                mult_start = 1;

-                               mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
-                               mult_in0 = op1 /* Rm */;
-                               mult_in1 = op2 /* Rs */;
+                               mult_acc0 = insn_2a[21] /* A */ ? op0_2a /* Rn */ : 32'h0;
+                               mult_in0 = op1_2a /* Rm */;
+                               mult_in1 = op2_2a /* Rs */;

                                $display("New MUL instruction");
                        end
                end
                                $display("New MUL instruction");
                        end
                end


@@ -213,14 +213,14 @@ module Execute(
        /* Miscellaneous cleanup. */
        always @(*)
        begin
        /* Miscellaneous cleanup. */
        always @(*)
        begin

-               next_outbubble = inbubble | flush | delayedflush;
+               next_bubble_3a = bubble_2a | flush | delayedflush;

 
 

-               jmp = 1'b0;
-               jmppc = 32'h00000000;
+               jmp_2a = 1'b0;
+               jmppc_2a = 32'h00000000;

 
 

-               casez (insn)
+               casez (insn_2a)

                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */

-                       next_outbubble = next_outbubble | !mult_done | !prevstall;
+                       next_bubble_3a = next_bubble_3a | !mult_done | !outstall_3a;

                `DECODE_ALU_MRS,        /* MRS (Transfer PSR to register) */
                `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
                `DECODE_ALU_MSR_FLAGS,  /* MSR (Transfer register or immediate to PSR, flag bits only) */
                `DECODE_ALU_MRS,        /* MRS (Transfer PSR to register) */
                `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
                `DECODE_ALU_MSR_FLAGS,  /* MSR (Transfer register or immediate to PSR, flag bits only) */


@@ -235,9 +235,9 @@ module Execute(
                begin end
                `DECODE_BRANCH:
                begin
                begin end
                `DECODE_BRANCH:
                begin

-                       if(!inbubble && !flush && !delayedflush && !outstall /* Let someone else take precedence. */) begin
-                               jmppc = pc + op0 + 32'h8;
-                               jmp = 1'b1;
+                       if(!bubble_2a && !flush && !delayedflush && !outstall_2a /* Let someone else take precedence. */) begin
+                               jmppc_2a = pc_2a + op0_2a + 32'h8;
+                               jmp_2a = 1'b1;

                        end
                end                     /* Branch */
                `DECODE_LDCSTC,         /* Coprocessor data transfer */
                        end
                end                     /* Branch */
                `DECODE_LDCSTC,         /* Coprocessor data transfer */

diff --git a/Issue.v b/Issue.v
index a8274ec55821b6970b6accf226e0bdfc9033f490..2aa810611a2bb7894b891100652d581cf25217b0 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -5,7 +5,7 @@ module Issue(
        input Nrst,     /* XXX not used yet */
        
        input stall_1a, /* pipeline control */
        input Nrst,     /* XXX not used yet */
        
        input stall_1a, /* pipeline control */

-       input flush,    /* XXX not used yet */
+       input flush_1a,

        
        input bubble_1a,        /* stage inputs */
        input [31:0] insn_1a,
        
        input bubble_1a,        /* stage inputs */
        input [31:0] insn_1a,


@@ -266,16 +266,16 @@ module Issue(
        wire waiting_cpsr_1a = use_cpsr & (cpsr_inflight_2a | cpsr_inflight_3a);
        wire waiting_regs_1a = |(use_regs & (regs_inflight_2a | regs_inflight_3a));
        wire waiting_1a = waiting_cpsr_1a | waiting_regs_1a;
        wire waiting_cpsr_1a = use_cpsr & (cpsr_inflight_2a | cpsr_inflight_3a);
        wire waiting_regs_1a = |(use_regs & (regs_inflight_2a | regs_inflight_3a));
        wire waiting_1a = waiting_cpsr_1a | waiting_regs_1a;

-       assign stall_0a = (waiting_1a && !bubble_1a && !flush) || stall_1a;
+       assign stall_0a = (waiting_1a && !bubble_1a && !flush_1a) || stall_1a;

 
 

-       reg delayedflush = 0;
+       reg delayedflush_1a = 0;

        always @(posedge clk/* or negedge Nrst*/)
                if (!Nrst)
        always @(posedge clk/* or negedge Nrst*/)
                if (!Nrst)

-                       delayedflush <= 0;
-               else if (flush && stall_0a /* halp! I can't do it now, maybe later? */)
-                       delayedflush <= 1;
+                       delayedflush_1a <= 0;
+               else if (flush_1a && stall_0a /* halp! I can't do it now, maybe later? */)
+                       delayedflush_1a <= 1;

                else if (!stall_0a /* anything has been handled this time around */)
                else if (!stall_0a /* anything has been handled this time around */)

-                       delayedflush <= 0;
+                       delayedflush_1a <= 0;

 
        /* Actually do the issue. */
        always @(posedge clk or negedge Nrst)
 
        /* Actually do the issue. */
        always @(posedge clk or negedge Nrst)


@@ -301,7 +301,7 @@ module Issue(
                        regs_inflight_3a <= regs_inflight_2a;
                        regs_inflight_2a <= (waiting_1a || bubble_1a || !condition_met_1a) ? 0 : def_regs;
                        
                        regs_inflight_3a <= regs_inflight_2a;
                        regs_inflight_2a <= (waiting_1a || bubble_1a || !condition_met_1a) ? 0 : def_regs;
                        

-                       bubble_2a <= bubble_1a | waiting_1a | !condition_met_1a | flush | delayedflush;
+                       bubble_2a <= bubble_1a | waiting_1a | !condition_met_1a | flush_1a | delayedflush_1a;

                        pc_2a <= pc_1a;
                        insn_2a <= insn_1a;
                end
                        pc_2a <= pc_1a;
                        insn_2a <= insn_1a;
                end

diff --git a/system.v b/system.v
index de3fd743b8a8574514c58a305c95854fd20e398b..071296c51c6a9bda104adb600febfd85608da9ed 100644 (file)
--- a/system.v
+++ b/system.v
@@ -116,12 +116,20 @@ module System(input clk, input rst
        /*AUTOWIRE*/
        // Beginning of automatic wires (for undeclared instantiated-module outputs)
        wire            bubble_1a;              // From fetch of Fetch.v
        /*AUTOWIRE*/
        // Beginning of automatic wires (for undeclared instantiated-module outputs)
        wire            bubble_1a;              // From fetch of Fetch.v

+       wire            bubble_2a;              // From issue of Issue.v
+       wire            carry_2a;               // From decode of Decode.v
+       wire [31:0]     cpsr_2a;                // From decode of Decode.v

        wire [31:0]     ic__rd_addr_0a;         // From fetch of Fetch.v
        wire [31:0]     ic__rd_data_1a;         // From icache of ICache.v
        wire            ic__rd_req_0a;          // From fetch of Fetch.v
        wire            ic__rd_wait_0a;         // From icache of ICache.v
        wire [31:0]     insn_1a;                // From fetch of Fetch.v
        wire [31:0]     ic__rd_addr_0a;         // From fetch of Fetch.v
        wire [31:0]     ic__rd_data_1a;         // From icache of ICache.v
        wire            ic__rd_req_0a;          // From fetch of Fetch.v
        wire            ic__rd_wait_0a;         // From icache of ICache.v
        wire [31:0]     insn_1a;                // From fetch of Fetch.v

+       wire [31:0]     insn_2a;                // From issue of Issue.v
+       wire [31:0]     op0_2a;                 // From decode of Decode.v
+       wire [31:0]     op1_2a;                 // From decode of Decode.v
+       wire [31:0]     op2_2a;                 // From decode of Decode.v

        wire [31:0]     pc_1a;                  // From fetch of Fetch.v
        wire [31:0]     pc_1a;                  // From fetch of Fetch.v

+       wire [31:0]     pc_2a;                  // From issue of Issue.v

        wire [31:0]     rf__rdata_0_1a;         // From regfile of RegFile.v
        wire [31:0]     rf__rdata_1_1a;         // From regfile of RegFile.v
        wire [31:0]     rf__rdata_2_1a;         // From regfile of RegFile.v
        wire [31:0]     rf__rdata_0_1a;         // From regfile of RegFile.v
        wire [31:0]     rf__rdata_1_1a;         // From regfile of RegFile.v
        wire [31:0]     rf__rdata_2_1a;         // From regfile of RegFile.v


@@ -129,6 +137,7 @@ module System(input clk, input rst
        wire [3:0]      rf__read_0_1a;          // From decode of Decode.v
        wire [3:0]      rf__read_1_1a;          // From decode of Decode.v
        wire [3:0]      rf__read_2_1a;          // From decode of Decode.v
        wire [3:0]      rf__read_0_1a;          // From decode of Decode.v
        wire [3:0]      rf__read_1_1a;          // From decode of Decode.v
        wire [3:0]      rf__read_2_1a;          // From decode of Decode.v

+       wire [31:0]     spsr_2a;                // From decode of Decode.v

        wire            stall_0a;               // From issue of Issue.v
        // End of automatics
 
        wire            stall_0a;               // From issue of Issue.v
        // End of automatics
 


@@ -187,7 +196,6 @@ module System(input clk, input rst
                .bus_ready(bus_ready_blockram));
 
        /* Fetch AUTO_TEMPLATE (
                .bus_ready(bus_ready_blockram));
 
        /* Fetch AUTO_TEMPLATE (

-               .stall_0a(stall_cause_issue),

                .jmp_0a(jmp),
                .jmppc_0a(jmppc),
                );
                .jmp_0a(jmp),
                .jmppc_0a(jmppc),
                );


@@ -205,31 +213,28 @@ module System(input clk, input rst
                    .Nrst               (Nrst),
                    .ic__rd_wait_0a     (ic__rd_wait_0a),
                    .ic__rd_data_1a     (ic__rd_data_1a[31:0]),
                    .Nrst               (Nrst),
                    .ic__rd_wait_0a     (ic__rd_wait_0a),
                    .ic__rd_data_1a     (ic__rd_data_1a[31:0]),

-                   .stall_0a           (stall_cause_issue),     // Templated
+                   .stall_0a           (stall_0a),

                    .jmp_0a             (jmp),                   // Templated
                    .jmppc_0a           (jmppc));                // Templated
        
        /* Issue AUTO_TEMPLATE (
                .stall_1a(stall_cause_execute),
                    .jmp_0a             (jmp),                   // Templated
                    .jmppc_0a           (jmppc));                // Templated
        
        /* Issue AUTO_TEMPLATE (
                .stall_1a(stall_cause_execute),

-               .flush(execute_out_backflush | writeback_out_backflush),
+               .flush_1a(execute_out_backflush | writeback_out_backflush),

                .cpsr_1a(writeback_out_cpsr),
                .cpsr_1a(writeback_out_cpsr),

-               .bubble_2a(bubble_out_issue),
-               .pc_2a(pc_out_issue),
-               .insn_2a(insn_out_issue),

                );
        */
        Issue issue(
                /*AUTOINST*/
                    // Outputs
                    .stall_0a           (stall_0a),
                );
        */
        Issue issue(
                /*AUTOINST*/
                    // Outputs
                    .stall_0a           (stall_0a),

-                   .bubble_2a          (bubble_out_issue),      // Templated
-                   .pc_2a              (pc_out_issue),          // Templated
-                   .insn_2a            (insn_out_issue),        // Templated
+                   .bubble_2a          (bubble_2a),
+                   .pc_2a              (pc_2a[31:0]),
+                   .insn_2a            (insn_2a[31:0]),

                    // Inputs
                    .clk                (clk),
                    .Nrst               (Nrst),
                    .stall_1a           (stall_cause_execute),   // Templated
                    // Inputs
                    .clk                (clk),
                    .Nrst               (Nrst),
                    .stall_1a           (stall_cause_execute),   // Templated

-                   .flush              (execute_out_backflush | writeback_out_backflush), // Templated
+                   .flush_1a           (execute_out_backflush | writeback_out_backflush), // Templated

                    .bubble_1a          (bubble_1a),
                    .insn_1a            (insn_1a[31:0]),
                    .pc_1a              (pc_1a[31:0]),
                    .bubble_1a          (bubble_1a),
                    .insn_1a            (insn_1a[31:0]),
                    .pc_1a              (pc_1a[31:0]),


@@ -264,25 +269,19 @@ module System(input clk, input rst
        
        /* Decode AUTO_TEMPLATE (
                .stall(stall_cause_execute),
        
        /* Decode AUTO_TEMPLATE (
                .stall(stall_cause_execute),

-               .incpsr(writeback_out_cpsr),
-               .inspsr(writeback_out_spsr),
-               .op0(decode_out_op0),
-               .op1(decode_out_op1),
-               .op2(decode_out_op2),
-               .carry(decode_out_carry),
-               .outcpsr(decode_out_cpsr),
-               .outspsr(decode_out_spsr),
+               .cpsr_1a(writeback_out_cpsr),
+               .spsr_1a(writeback_out_spsr),

                );
        */
        Decode decode(
                /*AUTOINST*/
                      // Outputs
                );
        */
        Decode decode(
                /*AUTOINST*/
                      // Outputs

-                     .op0              (decode_out_op0),        // Templated
-                     .op1              (decode_out_op1),        // Templated
-                     .op2              (decode_out_op2),        // Templated
-                     .carry            (decode_out_carry),      // Templated
-                     .outcpsr          (decode_out_cpsr),       // Templated
-                     .outspsr          (decode_out_spsr),       // Templated
+                     .op0_2a           (op0_2a[31:0]),
+                     .op1_2a           (op1_2a[31:0]),
+                     .op2_2a           (op2_2a[31:0]),
+                     .carry_2a         (carry_2a),
+                     .cpsr_2a          (cpsr_2a[31:0]),
+                     .spsr_2a          (spsr_2a[31:0]),

                      .rf__read_0_1a    (rf__read_0_1a[3:0]),
                      .rf__read_1_1a    (rf__read_1_1a[3:0]),
                      .rf__read_2_1a    (rf__read_2_1a[3:0]),
                      .rf__read_0_1a    (rf__read_0_1a[3:0]),
                      .rf__read_1_1a    (rf__read_1_1a[3:0]),
                      .rf__read_2_1a    (rf__read_2_1a[3:0]),


@@ -291,25 +290,64 @@ module System(input clk, input rst
                      .stall            (stall_cause_execute),   // Templated
                      .insn_1a          (insn_1a[31:0]),
                      .pc_1a            (pc_1a[31:0]),
                      .stall            (stall_cause_execute),   // Templated
                      .insn_1a          (insn_1a[31:0]),
                      .pc_1a            (pc_1a[31:0]),

-                     .incpsr           (writeback_out_cpsr),    // Templated
-                     .inspsr           (writeback_out_spsr),    // Templated
+                     .cpsr_1a          (writeback_out_cpsr),    // Templated
+                     .spsr_1a          (writeback_out_spsr),    // Templated

                      .rf__rdata_0_1a   (rf__rdata_0_1a[31:0]),
                      .rf__rdata_1_1a   (rf__rdata_1_1a[31:0]),
                      .rf__rdata_2_1a   (rf__rdata_2_1a[31:0]));
                      .rf__rdata_0_1a   (rf__rdata_0_1a[31:0]),
                      .rf__rdata_1_1a   (rf__rdata_1_1a[31:0]),
                      .rf__rdata_2_1a   (rf__rdata_2_1a[31:0]));

-       
+
+       /* Execute AUTO_TEMPLATE (
+               .stall_2a(stall_cause_memory),
+               .flush(writeback_out_backflush),
+               .outstall_2a(stall_cause_execute),
+               .bubble_3a(bubble_out_execute),
+               .write_reg_3a(execute_out_write_reg),
+               .write_num_3a(execute_out_write_num),
+               .write_data_3a(execute_out_write_data),
+               .jmp_2a(jmp_out_execute),
+               .jmppc_2a(jmppc_out_execute),
+               .pc_3a(pc_out_execute),
+               .insn_3a(insn_out_execute),
+               .op0_3a(execute_out_op0),
+               .op1_3a(execute_out_op1),
+               .op2_3a(execute_out_op2),
+               .outcpsr(execute_out_cpsr),
+               .outspsr(execute_out_spsr),
+               .outcpsrup(execute_out_cpsrup),
+               );
+       */      

        Execute execute(
        Execute execute(

-               .clk(clk), .Nrst(~rst),
-               .stall(stall_cause_memory), .flush(writeback_out_backflush),
-               .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
-               .cpsr(decode_out_cpsr), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
-               .op2(decode_out_op2), .carry(decode_out_carry),
-               .outstall(stall_cause_execute), .outbubble(bubble_out_execute),
-               .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
-               .write_data(execute_out_write_data),
-               .jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
-               .outpc(pc_out_execute), .outinsn(insn_out_execute),
-               .outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
-               .outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr), .outcpsrup(execute_out_cpsrup));
+               /*AUTOINST*/
+                       // Outputs
+                       .outstall_2a    (stall_cause_execute),   // Templated
+                       .bubble_3a      (bubble_out_execute),    // Templated
+                       .outcpsr        (execute_out_cpsr),      // Templated
+                       .outspsr        (execute_out_spsr),      // Templated
+                       .outcpsrup      (execute_out_cpsrup),    // Templated
+                       .write_reg_3a   (execute_out_write_reg), // Templated
+                       .write_num_3a   (execute_out_write_num), // Templated
+                       .write_data_3a  (execute_out_write_data), // Templated
+                       .jmppc_2a       (jmppc_out_execute),     // Templated
+                       .jmp_2a         (jmp_out_execute),       // Templated
+                       .pc_3a          (pc_out_execute),        // Templated
+                       .insn_3a        (insn_out_execute),      // Templated
+                       .op0_3a         (execute_out_op0),       // Templated
+                       .op1_3a         (execute_out_op1),       // Templated
+                       .op2_3a         (execute_out_op2),       // Templated
+                       // Inputs
+                       .clk            (clk),
+                       .Nrst           (Nrst),
+                       .stall_2a       (stall_cause_memory),    // Templated
+                       .flush          (writeback_out_backflush), // Templated
+                       .bubble_2a      (bubble_2a),
+                       .pc_2a          (pc_2a[31:0]),
+                       .insn_2a        (insn_2a[31:0]),
+                       .cpsr_2a        (cpsr_2a[31:0]),
+                       .spsr_2a        (spsr_2a[31:0]),
+                       .op0_2a         (op0_2a[31:0]),
+                       .op1_2a         (op1_2a[31:0]),
+                       .op2_2a         (op2_2a[31:0]),
+                       .carry_2a       (carry_2a));

        assign execute_out_backflush = jmp;
        
        assign cp_insn = insn_out_execute;
        assign execute_out_backflush = jmp;
        
        assign cp_insn = insn_out_execute;


@@ -356,8 +394,8 @@ module System(input clk, input rst
                clockno <= clockno + 1;
                $display("------------------------------------------------------------------------------");
                $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
                clockno <= clockno + 1;
                $display("------------------------------------------------------------------------------");
                $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);

-               $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
-               $display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
+               $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_0a, bubble_2a, insn_2a, pc_2a);
+               $display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, op0_2a, op1_2a, op2_2a, carry_2a);

                $display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
                $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
                $display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
                $display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
                $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
                $display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);