Global: More re-piping, and a bugfix for a bug recently introduced. (Regressions...
[firearm.git] / Execute.v
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1module Execute(
2 input clk,
3 input Nrst, /* XXX not used yet */
4
8c1ba494 5 input stall_2a,
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6 input flush,
7
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8 input bubble_2a,
9 input [31:0] pc_2a,
10 input [31:0] insn_2a,
11 input [31:0] cpsr_2a,
12 input [31:0] spsr_2a,
13 input [31:0] op0_2a,
14 input [31:0] op1_2a,
15 input [31:0] op2_2a,
16 input carry_2a,
5b3daee2 17
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18 output reg outstall_2a = 0,
19 output reg bubble_3a = 1,
6e3dfd79 20 output reg [31:0] outcpsr = 0,
cb0428b6 21 output reg [31:0] outspsr = 0,
fdecc897 22 output reg outcpsrup = 0,
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23 output reg write_reg_3a = 1'bx,
24 output reg [3:0] write_num_3a = 4'bxxxx,
25 output reg [31:0] write_data_3a = 32'hxxxxxxxx,
26 output reg [31:0] jmppc_2a,
27 output reg jmp_2a,
28 output reg [31:0] pc_3a,
29 output reg [31:0] insn_3a,
30 output reg [31:0] op0_3a, op1_3a, op2_3a
5b3daee2 31 );
5b3daee2 32
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33 reg mult_start;
34 reg [31:0] mult_acc0, mult_in0, mult_in1;
35 wire mult_done;
36 wire [31:0] mult_result;
37
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38 reg [31:0] alu_in0_2a, alu_in1_2a;
39 reg [3:0] alu_op_2a;
40 reg alu_setflags_2a;
41 wire [31:0] alu_result_2a, alu_outcpsr_2a;
42 wire alu_setres_2a;
732b7730 43
8c1ba494 44 reg next_bubble_3a;
cb0428b6 45 reg [31:0] next_outcpsr, next_outspsr;
fdecc897 46 reg next_outcpsrup;
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47
48 reg next_write_reg_3a;
49 reg [3:0] next_write_num_3a;
50 reg [31:0] next_write_data_3a;
149bcd1a 51
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52 Multiplier multiplier(
53 .clk(clk), .Nrst(Nrst),
54 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
55 .in1(mult_in1), .done(mult_done), .result(mult_result));
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56
57 ALU alu(
58 .clk(clk), .Nrst(Nrst),
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59 .in0(alu_in0_2a), .in1(alu_in1_2a), .cpsr(cpsr_2a), .op(alu_op_2a),
60 .setflags(alu_setflags_2a), .shifter_carry(carry_2a),
61 .result(alu_result_2a), .cpsr_out(alu_outcpsr_2a), .setres(alu_setres_2a));
b770ec9a 62
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63 always @(posedge clk)
64 begin
8c1ba494 65 if (!stall_2a)
732b7730 66 begin
8c1ba494 67 bubble_3a <= next_bubble_3a;
732b7730 68 outcpsr <= next_outcpsr;
cb0428b6 69 outspsr <= next_outspsr;
fdecc897 70 outcpsrup <= next_outcpsrup;
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71 write_reg_3a <= next_write_reg_3a;
72 write_num_3a <= next_write_num_3a;
73 write_data_3a <= next_write_data_3a;
74 pc_3a <= pc_2a;
75 insn_3a <= insn_2a;
76 op0_3a <= op0_2a;
77 op1_3a <= op1_2a;
78 op2_3a <= op2_2a;
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79 end
80 end
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81
82 reg delayedflush = 0;
83 always @(posedge clk)
8c1ba494 84 if (flush && outstall_2a /* halp! I can't do it now, maybe later? */)
b770ec9a 85 delayedflush <= 1;
8c1ba494 86 else if (!outstall_2a /* anything has been handled this time around */)
b770ec9a 87 delayedflush <= 0;
2b091cd4 88
8c1ba494 89 reg outstall_3a = 0;
af096d96 90 always @(posedge clk)
8c1ba494 91 outstall_3a <= outstall_2a;
3ccca009 92
2b091cd4 93 always @(*)
732b7730 94 begin
8c1ba494 95 outstall_2a = stall_2a;
3ccca009 96
8c1ba494 97 casez (insn_2a)
3ccca009 98 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
8c1ba494 99 outstall_2a = outstall_2a | ((!outstall_3a | !mult_done) && !bubble_2a);
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100 endcase
101 end
102
103 /* ALU inputs */
104 always @(*)
105 begin
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106 alu_in0_2a = op0_2a;
107 alu_in1_2a = op1_2a;
108 alu_op_2a = insn_2a[24:21];
109 alu_setflags_2a = insn_2a[20] /* S */;
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110 end
111
112 /* Register outputs */
113 always @(*)
114 begin
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115 next_outcpsr = cpsr_2a;
116 next_outspsr = spsr_2a;
fdecc897 117 next_outcpsrup = 0;
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118 next_write_reg_3a = 0;
119 next_write_num_3a = 4'hx;
120 next_write_data_3a = 32'hxxxxxxxx;
3ccca009 121
8c1ba494 122 casez(insn_2a)
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123 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
124 begin
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125 next_outcpsr = insn_2a[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr_2a[28] /* V */, cpsr_2a[27:0]} : cpsr_2a;
126 next_outcpsrup = insn_2a[20] /* S */;
127 next_write_reg_3a = 1;
128 next_write_num_3a = insn_2a[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
129 next_write_data_3a = mult_result;
af096d96 130 end
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131 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
132 begin
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133 next_write_reg_3a = 1;
134 next_write_num_3a = insn_2a[15:12];
135 if (insn_2a[22] /* Ps */)
136 next_write_data_3a = spsr_2a;
cb0428b6 137 else
8c1ba494 138 next_write_data_3a = cpsr_2a;
cb0428b6 139 end
2b091cd4 140 `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
cb0428b6 141 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
fdecc897 142 begin
8c1ba494 143 if ((cpsr_2a[4:0] == `MODE_USR) || (insn_2a[16] /* that random bit */ == 1'b0)) /* flags only */
cb0428b6 144 begin
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145 if (insn_2a[22] /* Ps */)
146 next_outspsr = {op0_2a[31:29], spsr_2a[28:0]};
cb0428b6 147 else
8c1ba494 148 next_outcpsr = {op0_2a[31:29], cpsr_2a[28:0]};
cb0428b6 149 end else begin
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150 if (insn_2a[22] /* Ps */)
151 next_outspsr = op0_2a;
cb0428b6 152 else
8c1ba494 153 next_outcpsr = op0_2a;
cb0428b6 154 end
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155 next_outcpsrup = 1;
156 end
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157 `DECODE_ALU_SWP, /* Atomic swap */
158 `DECODE_ALU_BX, /* Branch */
159 `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
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160 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
161 begin end
162 `DECODE_ALU: /* ALU */
163 begin
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164 if (alu_setres_2a) begin
165 next_write_reg_3a = 1;
166 next_write_num_3a = insn_2a[15:12] /* Rd */;
167 next_write_data_3a = alu_result_2a;
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168 end
169
8c1ba494 170 if (insn_2a[20] /* S */) begin
3ccca009 171 next_outcpsrup = 1;
8c1ba494 172 next_outcpsr = ((insn_2a[15:12] == 4'b1111) && insn_2a[20]) ? spsr_2a : alu_outcpsr_2a;
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173 end
174 end
175 `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
176 `DECODE_LDRSTR, /* Single data transfer */
177 `DECODE_LDMSTM: /* Block data transfer */
178 begin end
179 `DECODE_BRANCH: /* Branch */
180 begin
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181 if(insn_2a[24] /* L */) begin
182 next_write_reg_3a = 1;
183 next_write_num_3a = 4'hE; /* link register */
184 next_write_data_3a = pc_2a + 32'h4;
3ccca009 185 end
732b7730 186 end
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187 endcase
188 end
189
190 /* Multiplier inputs */
191 always @(*)
192 begin
193 mult_start = 0;
194 mult_acc0 = 32'hxxxxxxxx;
195 mult_in0 = 32'hxxxxxxxx;
196 mult_in1 = 32'hxxxxxxxx;
197
8c1ba494 198 casez(insn_2a)
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199 `DECODE_ALU_MULT:
200 begin
8c1ba494 201 if (!outstall_3a /* i.e., this is a new one */ && !bubble_2a /* i.e., this is a real one */)
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202 begin
203 mult_start = 1;
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204 mult_acc0 = insn_2a[21] /* A */ ? op0_2a /* Rn */ : 32'h0;
205 mult_in0 = op1_2a /* Rm */;
206 mult_in1 = op2_2a /* Rs */;
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207 $display("New MUL instruction");
208 end
209 end
210 endcase
211 end
212
213 /* Miscellaneous cleanup. */
214 always @(*)
215 begin
8c1ba494 216 next_bubble_3a = bubble_2a | flush | delayedflush;
3ccca009 217
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218 jmp_2a = 1'b0;
219 jmppc_2a = 32'h00000000;
3ccca009 220
8c1ba494 221 casez (insn_2a)
3ccca009 222 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
8c1ba494 223 next_bubble_3a = next_bubble_3a | !mult_done | !outstall_3a;
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224 `DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */
225 `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
226 `DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */
227 `DECODE_ALU_SWP, /* Atomic swap */
228 `DECODE_ALU_BX, /* Branch */
229 `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
230 `DECODE_ALU_HDATA_IMM, /* Halfword transfer - immediate offset */
231 `DECODE_ALU, /* ALU */
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232 `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
233 `DECODE_LDRSTR, /* Single data transfer */
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234 `DECODE_LDMSTM: /* Block data transfer */
235 begin end
236 `DECODE_BRANCH:
237 begin
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238 if(!bubble_2a && !flush && !delayedflush && !outstall_2a /* Let someone else take precedence. */) begin
239 jmppc_2a = pc_2a + op0_2a + 32'h8;
240 jmp_2a = 1'b1;
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241 end
242 end /* Branch */
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243 `DECODE_LDCSTC, /* Coprocessor data transfer */
244 `DECODE_CDP, /* Coprocessor data op */
245 `DECODE_MRCMCR, /* Coprocessor register transfer */
246 `DECODE_SWI: /* SWI */
247 begin end
248 default: /* X everything else out */
249 begin end
250 endcase
732b7730 251 end
5b3daee2 252endmodule
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253
254module Multiplier(
255 input clk,
256 input Nrst, /* XXX not used yet */
257
258 input start,
259 input [31:0] acc0,
260 input [31:0] in0,
261 input [31:0] in1,
262
263 output reg done = 0,
264 output reg [31:0] result);
265
266 reg [31:0] bitfield;
267 reg [31:0] multiplicand;
268 reg [31:0] acc;
269
270 always @(posedge clk)
271 begin
272 if (start) begin
273 bitfield <= in0;
274 multiplicand <= in1;
275 acc <= acc0;
276 done <= 0;
277 end else begin
278 bitfield <= {2'b00, bitfield[31:2]};
279 multiplicand <= {multiplicand[29:0], 2'b00};
280 acc <= acc +
281 (bitfield[0] ? multiplicand : 0) +
282 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
283 if (bitfield == 0) begin
284 result <= acc;
285 done <= 1;
286 end
287 end
288 end
289endmodule
879a3986 290
879a3986
CL
291module ALU(
292 input clk,
293 input Nrst, /* XXX not used yet */
294
295 input [31:0] in0,
296 input [31:0] in1,
297 input [31:0] cpsr,
298 input [3:0] op,
299 input setflags,
300 input shifter_carry,
301
302 output reg [31:0] result,
303 output reg [31:0] cpsr_out,
732b7730 304 output reg setres
879a3986 305);
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306 reg [31:0] res;
307 reg flag_n, flag_z, flag_c, flag_v;
879a3986 308 wire [32:0] sum, diff, rdiff;
793482e9 309 wire sum_v, diff_v, rdiff_v;
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310
311 assign sum = {1'b0, in0} + {1'b0, in1};
312 assign diff = {1'b0, in0} - {1'b0, in1};
a4c270c7 313 assign rdiff = {1'b0, in1} - {1'b0, in0};
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CL
314 assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
315 assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
316 assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
879a3986 317
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318 always @(*) begin
319 res = 32'hxxxxxxxx;
320 setres = 1'bx;
321 flag_c = cpsr[`CPSR_C];
322 flag_v = cpsr[`CPSR_V];
323 case(op)
324 `ALU_AND: begin
732b7730 325 result = in0 & in1;
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326 flag_c = shifter_carry;
327 setres = 1'b1;
328 end
329 `ALU_EOR: begin
732b7730 330 result = in0 ^ in1;
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331 flag_c = shifter_carry;
332 setres = 1'b1;
333 end
334 `ALU_SUB: begin
732b7730 335 {flag_c, result} = diff;
1bc060d9 336 flag_c = !flag_c;
793482e9 337 flag_v = diff_v;
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338 setres = 1'b1;
339 end
340 `ALU_RSB: begin
732b7730 341 {flag_c, result} = rdiff;
1bc060d9 342 flag_c = !flag_c;
793482e9 343 flag_v = rdiff_v;
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344 setres = 1'b1;
345 end
346 `ALU_ADD: begin
732b7730 347 {flag_c, result} = sum;
793482e9 348 flag_v = sum_v;
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349 setres = 1'b1;
350 end
351 `ALU_ADC: begin
732b7730 352 {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
793482e9 353 flag_v = sum_v | (~sum[31] & result[31]);
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354 setres = 1'b1;
355 end
356 `ALU_SBC: begin
732b7730 357 {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
1bc060d9 358 flag_c = !flag_c;
793482e9 359 flag_v = diff_v | (diff[31] & ~result[31]);
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360 setres = 1'b1;
361 end
362 `ALU_RSC: begin
732b7730 363 {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
1bc060d9 364 flag_c = !flag_c;
793482e9 365 flag_v = rdiff_v | (rdiff[31] & ~result[31]);
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366 setres = 1'b1;
367 end
368 `ALU_TST: begin
732b7730 369 result = in0 & in1;
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370 flag_c = shifter_carry;
371 setres = 1'b0;
372 end
373 `ALU_TEQ: begin
732b7730 374 result = in0 ^ in1;
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375 flag_c = shifter_carry;
376 setres = 1'b0;
377 end
378 `ALU_CMP: begin
732b7730 379 {flag_c, result} = diff;
1bc060d9 380 flag_c = !flag_c;
793482e9 381 flag_v = diff_v;
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382 setres = 1'b0;
383 end
384 `ALU_CMN: begin
732b7730 385 {flag_c, result} = sum;
793482e9 386 flag_v = sum_v;
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387 setres = 1'b0;
388 end
389 `ALU_ORR: begin
732b7730 390 result = in0 | in1;
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391 flag_c = shifter_carry;
392 setres = 1'b1;
393 end
394 `ALU_MOV: begin
732b7730 395 result = in1;
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396 flag_c = shifter_carry;
397 setres = 1'b1;
398 end
399 `ALU_BIC: begin
732b7730 400 result = in0 & (~in1);
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401 flag_c = shifter_carry;
402 setres = 1'b1;
403 end
404 `ALU_MVN: begin
732b7730 405 result = ~in1;
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406 flag_c = shifter_carry;
407 setres = 1'b1;
408 end
409 endcase
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410
411 flag_z = (result == 0);
412 flag_n = result[31];
413
414 cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
879a3986 415 end
879a3986 416endmodule
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