Nicer dump information.
[firearm.git] / Decode.v
1 `include "ARM_Constants.v"
2
3 module Decode(
4         input clk,
5         input [31:0] insn,
6         input [31:0] inpc,
7         input [31:0] incpsr,
8         output reg [31:0] op0,
9         output reg [31:0] op1,
10         output reg [31:0] op2,
11         output reg [31:0] outcpsr,
12
13         output [3:0] read_0,
14         output [3:0] read_1,
15         output [3:0] read_2,
16         input [31:0] rdata_0,
17         input [31:0] rdata_1,
18         input [31:0] rdata_2
19         );
20
21         wire [31:0] regs0, regs1, regs2, rpc;
22         wire [31:0] op1_res, cpsr;
23
24         /* shifter stuff */
25         wire [31:0] shift_oper;
26         wire [31:0] shift_res;
27         wire shift_cflag_out;
28
29         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
30         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
31         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
32
33         IHATEARMSHIFT blowme(.insn(insn),
34                              .operand(regs1),
35                              .reg_amt(regs2),
36                              .cflag_in(incpsr[`CPSR_C]),
37                              .res(shift_res),
38                              .cflag_out(shift_cflag_out));
39         
40         always @(*)
41                 casez (insn)
42                 32'b????000000??????????????1001????,   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
43 //              32'b????00001???????????????1001????,   /* Multiply long */
44                 32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
45                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
46                 32'b????00?10?1010001111????????????,   /* MSR (Transfer register or immediate to PSR, flag bits only) */
47                 32'b????00010?00????????00001001????,   /* Atomic swap */
48                 32'b????000100101111111111110001????,   /* Branch */
49                 32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
50                 32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
51                 32'b????011????????????????????1????,   /* Undefined. I hate ARM */
52                 32'b????01??????????????????????????,   /* Single data transfer */
53                 32'b????100?????????????????????????,   /* Block data transfer */
54                 32'b????101?????????????????????????,   /* Branch */
55                 32'b????110?????????????????????????,   /* Coprocessor data transfer */
56                 32'b????1110???????????????????0????,   /* Coprocessor data op */
57                 32'b????1110???????????????????1????,   /* Coprocessor register transfer */
58                 32'b????1111????????????????????????:   /* SWI */
59                         rpc = inpc - 8;
60                 32'b????00??????????????????????????:   /* ALU */
61                         rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
62                 default:                                /* X everything else out */
63                         rpc = 32'hxxxxxxxx;
64                 endcase
65
66         always @ (*) begin
67                 casez (insn)
68                 32'b????000000??????????????1001????: begin /* Multiply */
69                         read_0 = insn[15:12]; /* Rn */
70                         read_1 = insn[3:0];   /* Rm */
71                         read_2 = insn[11:8];  /* Rs */
72                         op1_res = regs1;
73                         cpsr = incpsr;
74                 end
75 /*
76                 32'b????00001???????????????1001????: begin * Multiply long *
77                         read_0 = insn[11:8]; * Rn *
78                         read_1 = insn[3:0];  * Rm *
79                         read_2 = 4'b0;       * anyus *
80                         op1_res = regs1;
81                 end
82 */
83                 32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
84                         cpsr = incpsr;
85                 end
86                 32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
87                         cpsr = incpsr;
88                 end
89                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
90                         cpsr = incpsr;
91                 end
92                 32'b????00??????????????????????????: begin /* ALU */
93                         read_0 = insn[19:16]; /* Rn */
94                         read_1 = insn[3:0];   /* Rm */
95                         read_2 = insn[11:8];  /* Rs for shift */
96                         if(insn[25]) begin     /* the constant case */
97                                 cpsr = incpsr;
98                                 op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
99                         end else begin
100                                 cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
101                                 op1_res = shift_res;
102                         end
103                 end
104                 32'b????00010?00????????00001001????: begin /* Atomic swap */
105                         read_0 = insn[19:16]; /* Rn */
106                         read_1 = insn[3:0];   /* Rm */
107                         read_2 = 4'b0;        /* anyus */
108                         op1_res = regs1;
109                 end
110                 32'b????000100101111111111110001????: begin /* Branch and exchange */
111                         read_0 = insn[3:0];   /* Rn */
112                         cpsr = incpsr;
113                 end
114                 32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
115                         read_0 = insn[19:16];
116                         read_1 = insn[3:0];
117                         read_2 = 4'b0;
118                         op1_res = regs1;
119                         cpsr = incpsr;
120                 end
121                 32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
122                         read_0 = insn[19:16];
123                         read_1 = insn[3:0];
124                         op1_res = {24'b0, insn[11:8], insn[3:0]};
125                         cpsr = incpsr;
126                 end
127                 32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
128                         /* eat shit */
129                 end
130                 32'b????01??????????????????????????: begin /* Single data transfer */
131                         read_0 = insn[19:16]; /* Rn */
132                         read_1 = insn[3:0];   /* Rm */
133                         if(insn[25]) begin
134                                 op1_res = {20'b0, insn[11:0]};
135                                 cpsr = incpsr;
136                         end else begin
137                                 op1_res = shift_res;
138                                 cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
139                         end
140                 end
141                 32'b????100?????????????????????????: begin /* Block data transfer */
142                         read_0 = insn[19:16];
143                         op1_res = {16'b0, insn[15:0]};
144                         cpsr = incpsr;
145                 end
146                 32'b????101?????????????????????????: begin /* Branch */
147                         op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};
148                         cpsr = incpsr;
149                 end
150                 32'b????110?????????????????????????: begin /* Coprocessor data transfer */
151                         read_0 = insn[19:16];
152                         op1_res = {24'b0, insn[7:0]};
153                         cpsr = incpsr;
154                 end
155                 32'b????1110???????????????????0????: begin /* Coprocessor data op */
156                         cpsr = incpsr;
157                 end
158                 32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
159                         cpsr = incpsr;
160                 end
161                 32'b????1111????????????????????????: begin /* SWI */
162                         cpsr = incpsr;
163                 end
164                 default: begin end
165                 endcase
166         end
167
168         always @ (posedge clk) begin
169                 op0 <= regs0;   /* Rn - always */
170                 op1 <= op1_res; /* 'operand 2' - Rm */
171                 op2 <= regs2;   /* thirdedge - Rs */
172                 outcpsr <= cpsr;
173         end
174
175 endmodule
176
177 module IHATEARMSHIFT(
178         input [31:0] insn,
179         input [31:0] operand,
180         input [31:0] reg_amt,
181         input cflag_in,
182         output [31:0] res,
183         output cflag_out
184 );
185         wire [5:0] shift_amt;
186         wire elanus;
187
188
189         /* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */
190         always @(*)
191                 if(insn[4]) begin
192                         shift_amt = {|reg_amt[7:5], reg_amt[4:0]};
193                         elanus = 1'b1;
194                 end else begin
195                         shift_amt = {insn[11:7] == 5'b0, insn[11:7]};
196                         elanus = 1'b0;
197                 end
198         
199         always @(*)
200                 case (insn[6:5]) /* shift type */
201                 `SHIFT_LSL: begin
202                         {cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]};
203                 end
204                 `SHIFT_LSR: begin
205                         {res, cflag_out} = {operand, cflag_in} >> shift_amt;
206                 end
207                 `SHIFT_ASR: begin
208                         {res, cflag_out} = {operand, cflag_in} >> shift_amt | (operand[31] ? ~(33'h1FFFFFFFF >> shift_amt) : 33'b0);
209                 end
210                 `SHIFT_ROR: begin
211                         if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
212                                 res = {cflag_in, operand[31:1]};
213                                 cflag_out = operand[0];
214                         end else if(shift_amt == 6'b0) begin
215                                 res = operand;
216                                 cflag_out = cflag_in;
217                         end else begin
218                                 res = operand >> shift_amt[4:0] | operand << (5'b0 - shift_amt[4:0]);
219                                 cflag_out = operand[shift_amt[4:0] - 5'b1];
220                         end
221                 end
222                 endcase
223 endmodule
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