Add fetch module
[firearm.git] / fetch.v
CommitLineData
bd073175
JW
1module Fetch(
2 input clk,
3 input Nrst,
4
5 output wire [31:0] rd_addr,
6 output wire rd_req,
7 input rd_wait,
8 input [31:0] rd_data,
9
10 input stall,
11 input jmp,
12 input [31:0] jmppc;
13 output wire bubble,
14 output wire [31:0] insn,
15 output reg [31:0] pc);
16
17 reg [31:0] prevpc;
18 initial
19 prevpc <= 32'h0;
20 always @(negedge Nrst)
21 prevpc <= 32'h0;
22
23 always @(*)
24 if (!Nrst)
25 pc <= 32'h0;
26 else if (stall) /* don't change any internal state */
27 pc <= prevpc;
28 else if (jmp)
29 pc <= jmppc;
30 else
31 pc <= prevpc + 32'h4;
32
33 assign bubble = stall | rd_wait;
34 assign rd_addr = pc;
35 assign rd_req = !stall;
36 assign insn = rd_data;
37
38 always @(posedge clk)
39 prevpc <= pc;
40endmodule
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