Execute: fix rdiff
[firearm.git] / Execute.v
CommitLineData
5b3daee2
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1module Execute(
2 input clk,
3 input Nrst, /* XXX not used yet */
4
5 input stall,
6 input flush,
7
8 input inbubble,
9 input [31:0] pc,
10 input [31:0] insn,
11 input [31:0] cpsr,
cb0428b6 12 input [31:0] spsr,
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13 input [31:0] op0,
14 input [31:0] op1,
15 input [31:0] op2,
16 input carry,
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17
18 output reg outstall = 0,
bc572c5f 19 output reg outbubble = 1,
6e3dfd79 20 output reg [31:0] outcpsr = 0,
cb0428b6 21 output reg [31:0] outspsr = 0,
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22 output reg write_reg = 1'bx,
23 output reg [3:0] write_num = 4'bxxxx,
314dac21 24 output reg [31:0] write_data = 32'hxxxxxxxx,
149bcd1a 25 output reg [31:0] jmppc,
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26 output reg jmp,
27 output reg [31:0] outpc,
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28 output reg [31:0] outinsn,
29 output reg [31:0] outop0, outop1, outop2
5b3daee2 30 );
5b3daee2 31
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32 reg mult_start;
33 reg [31:0] mult_acc0, mult_in0, mult_in1;
34 wire mult_done;
35 wire [31:0] mult_result;
36
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37 reg [31:0] alu_in0, alu_in1;
38 reg [3:0] alu_op;
39 reg alu_setflags;
6e3dfd79 40 wire [31:0] alu_result, alu_outcpsr;
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41 wire alu_setres;
42
43 reg next_outbubble;
cb0428b6 44 reg [31:0] next_outcpsr, next_outspsr;
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45 reg next_write_reg;
46 reg [3:0] next_write_num;
149bcd1a 47
732b7730 48 reg [31:0] next_write_data;
149bcd1a 49
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JW
50 Multiplier multiplier(
51 .clk(clk), .Nrst(Nrst),
52 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
53 .in1(mult_in1), .done(mult_done), .result(mult_result));
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54
55 ALU alu(
56 .clk(clk), .Nrst(Nrst),
57 .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
58 .setflags(alu_setflags), .shifter_carry(carry),
732b7730 59 .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
b770ec9a 60
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61 always @(posedge clk)
62 begin
63 if (!stall)
64 begin
65 outbubble <= next_outbubble;
66 outcpsr <= next_outcpsr;
cb0428b6 67 outspsr <= next_outspsr;
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68 write_reg <= next_write_reg;
69 write_num <= next_write_num;
70 write_data <= next_write_data;
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71 outpc <= pc;
72 outinsn <= insn;
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73 outop0 <= op0;
74 outop1 <= op1;
75 outop2 <= op2;
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76 end
77 end
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78
79 reg delayedflush = 0;
80 always @(posedge clk)
81 if (flush && outstall /* halp! I can't do it now, maybe later? */)
82 delayedflush <= 1;
83 else if (!outstall /* anything has been handled this time around */)
84 delayedflush <= 0;
2b091cd4 85
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86 reg prevstall = 0;
87 always @(posedge clk)
88 prevstall <= outstall;
89
2b091cd4 90 always @(*)
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91 begin
92 outstall = stall;
b770ec9a 93 next_outbubble = inbubble | flush | delayedflush;
732b7730 94 next_outcpsr = cpsr;
cb0428b6 95 next_outspsr = spsr;
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96 next_write_reg = 0;
97 next_write_num = 4'hx;
98 next_write_data = 32'hxxxxxxxx;
149bcd1a 99
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100 mult_start = 0;
101 mult_acc0 = 32'hxxxxxxxx;
102 mult_in0 = 32'hxxxxxxxx;
103 mult_in1 = 32'hxxxxxxxx;
149bcd1a 104
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105 alu_in0 = 32'hxxxxxxxx;
106 alu_in1 = 32'hxxxxxxxx;
107 alu_op = 4'hx; /* hax! */
108 alu_setflags = 1'bx;
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CL
109
110 jmp = 1'b0;
ab7ee9fc 111 jmppc = 32'h00000000;
149bcd1a 112
2b091cd4 113 casez (insn)
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114 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
115 begin
116 if (!prevstall && !inbubble)
117 begin
118 mult_start = 1;
119 mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
120 mult_in0 = op1 /* Rm */;
121 mult_in1 = op2 /* Rs */;
122 $display("New MUL instruction");
123 end
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124 outstall = outstall | ((!prevstall | !mult_done) && !inbubble);
125 next_outbubble = next_outbubble | !mult_done | !prevstall;
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126 next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
127 next_write_reg = 1;
128 next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
129 next_write_data = mult_result;
130 end
2b091cd4 131// `DECODE_ALU_MUL_LONG, /* Multiply long */
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132 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
133 begin
134 next_write_reg = 1;
135 next_write_num = insn[15:12];
136 if (insn[22] /* Ps */)
137 next_write_data = spsr;
138 else
139 next_write_data = cpsr;
140 end
2b091cd4 141 `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
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142 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
143 if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0)) /* flags only */
144 begin
145 if (insn[22] /* Ps */)
146 next_outspsr = {op0[31:29], spsr[28:0]};
147 else
148 next_outcpsr = {op0[31:29], cpsr[28:0]};
149 end else begin
150 if (insn[22] /* Ps */)
151 next_outspsr = op0;
152 else
153 next_outcpsr = op0;
154 end
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155 `DECODE_ALU_SWP, /* Atomic swap */
156 `DECODE_ALU_BX, /* Branch */
157 `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
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158 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
159 begin end
160 `DECODE_ALU: /* ALU */
161 begin
162 alu_in0 = op0;
163 alu_in1 = op1;
164 alu_op = insn[24:21];
cb0428b6 165 alu_setflags = insn[20] /* S */;
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166
167 if (alu_setres) begin
168 next_write_reg = 1;
169 next_write_num = insn[15:12] /* Rd */;
170 next_write_data = alu_result;
171 end
172
cb0428b6 173 next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
732b7730 174 end
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175 `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
176 `DECODE_LDRSTR, /* Single data transfer */
314dac21
CL
177 `DECODE_LDMSTM: /* Block data transfer */
178 begin end
179 `DECODE_BRANCH:
180 begin
b770ec9a 181 if(!inbubble && !flush && !delayedflush) begin
f8bf38ca
CL
182 jmppc = pc + op0 + 32'h8;
183 if(insn[24]) begin
184 next_write_reg = 1;
185 next_write_num = 4'hE; /* link register */
dbf45af6 186 next_write_data = pc + 32'h4;
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CL
187 end
188 jmp = 1'b1;
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CL
189 end
190 end /* Branch */
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191 `DECODE_LDCSTC, /* Coprocessor data transfer */
192 `DECODE_CDP, /* Coprocessor data op */
193 `DECODE_MRCMCR, /* Coprocessor register transfer */
194 `DECODE_SWI: /* SWI */
195 begin end
196 default: /* X everything else out */
197 begin end
198 endcase
732b7730 199 end
5b3daee2 200endmodule
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201
202module Multiplier(
203 input clk,
204 input Nrst, /* XXX not used yet */
205
206 input start,
207 input [31:0] acc0,
208 input [31:0] in0,
209 input [31:0] in1,
210
211 output reg done = 0,
212 output reg [31:0] result);
213
214 reg [31:0] bitfield;
215 reg [31:0] multiplicand;
216 reg [31:0] acc;
217
218 always @(posedge clk)
219 begin
220 if (start) begin
221 bitfield <= in0;
222 multiplicand <= in1;
223 acc <= acc0;
224 done <= 0;
225 end else begin
226 bitfield <= {2'b00, bitfield[31:2]};
227 multiplicand <= {multiplicand[29:0], 2'b00};
228 acc <= acc +
229 (bitfield[0] ? multiplicand : 0) +
230 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
231 if (bitfield == 0) begin
232 result <= acc;
233 done <= 1;
234 end
235 end
236 end
237endmodule
879a3986 238
879a3986
CL
239module ALU(
240 input clk,
241 input Nrst, /* XXX not used yet */
242
243 input [31:0] in0,
244 input [31:0] in1,
245 input [31:0] cpsr,
246 input [3:0] op,
247 input setflags,
248 input shifter_carry,
249
250 output reg [31:0] result,
251 output reg [31:0] cpsr_out,
732b7730 252 output reg setres
879a3986 253);
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254 reg [31:0] res;
255 reg flag_n, flag_z, flag_c, flag_v;
879a3986 256 wire [32:0] sum, diff, rdiff;
793482e9 257 wire sum_v, diff_v, rdiff_v;
879a3986
CL
258
259 assign sum = {1'b0, in0} + {1'b0, in1};
260 assign diff = {1'b0, in0} - {1'b0, in1};
a4c270c7 261 assign rdiff = {1'b0, in1} - {1'b0, in0};
793482e9
CL
262 assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
263 assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
264 assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
879a3986 265
879a3986
CL
266 always @(*) begin
267 res = 32'hxxxxxxxx;
268 setres = 1'bx;
269 flag_c = cpsr[`CPSR_C];
270 flag_v = cpsr[`CPSR_V];
271 case(op)
272 `ALU_AND: begin
732b7730 273 result = in0 & in1;
879a3986
CL
274 flag_c = shifter_carry;
275 setres = 1'b1;
276 end
277 `ALU_EOR: begin
732b7730 278 result = in0 ^ in1;
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CL
279 flag_c = shifter_carry;
280 setres = 1'b1;
281 end
282 `ALU_SUB: begin
732b7730 283 {flag_c, result} = diff;
793482e9 284 flag_v = diff_v;
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CL
285 setres = 1'b1;
286 end
287 `ALU_RSB: begin
732b7730 288 {flag_c, result} = rdiff;
793482e9 289 flag_v = rdiff_v;
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CL
290 setres = 1'b1;
291 end
292 `ALU_ADD: begin
732b7730 293 {flag_c, result} = sum;
793482e9 294 flag_v = sum_v;
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CL
295 setres = 1'b1;
296 end
297 `ALU_ADC: begin
732b7730 298 {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
793482e9 299 flag_v = sum_v | (~sum[31] & result[31]);
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CL
300 setres = 1'b1;
301 end
302 `ALU_SBC: begin
732b7730 303 {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
793482e9 304 flag_v = diff_v | (diff[31] & ~result[31]);
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CL
305 setres = 1'b1;
306 end
307 `ALU_RSC: begin
732b7730 308 {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
793482e9 309 flag_v = rdiff_v | (rdiff[31] & ~result[31]);
879a3986
CL
310 setres = 1'b1;
311 end
312 `ALU_TST: begin
732b7730 313 result = in0 & in1;
879a3986
CL
314 flag_c = shifter_carry;
315 setres = 1'b0;
316 end
317 `ALU_TEQ: begin
732b7730 318 result = in0 ^ in1;
879a3986
CL
319 flag_c = shifter_carry;
320 setres = 1'b0;
321 end
322 `ALU_CMP: begin
732b7730 323 {flag_c, result} = diff;
793482e9 324 flag_v = diff_v;
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CL
325 setres = 1'b0;
326 end
327 `ALU_CMN: begin
732b7730 328 {flag_c, result} = sum;
793482e9 329 flag_v = sum_v;
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CL
330 setres = 1'b0;
331 end
332 `ALU_ORR: begin
732b7730 333 result = in0 | in1;
879a3986
CL
334 flag_c = shifter_carry;
335 setres = 1'b1;
336 end
337 `ALU_MOV: begin
732b7730 338 result = in1;
879a3986
CL
339 flag_c = shifter_carry;
340 setres = 1'b1;
341 end
342 `ALU_BIC: begin
732b7730 343 result = in0 & (~in1);
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CL
344 flag_c = shifter_carry;
345 setres = 1'b1;
346 end
347 `ALU_MVN: begin
732b7730 348 result = ~in1;
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349 flag_c = shifter_carry;
350 setres = 1'b1;
351 end
352 endcase
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353
354 flag_z = (result == 0);
355 flag_n = result[31];
356
357 cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
879a3986 358 end
879a3986 359endmodule
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