Ok, move read_0, read_1, read_2 back into a unified block again.
[firearm.git] / Decode.v
1 `include "ARM_Constants.v"
2
3 module Decode(
4         input clk,
5         input [31:0] insn,
6         input [31:0] inpc,
7         input [31:0] incpsr,
8         output reg [31:0] op0,
9         output reg [31:0] op1,
10         output reg [31:0] op2,
11         output reg [31:0] outcpsr,
12
13         output [3:0] read_0,
14         output [3:0] read_1,
15         output [3:0] read_2,
16         input [31:0] rdata_0,
17         input [31:0] rdata_1,
18         input [31:0] rdata_2
19         );
20
21         wire [31:0] regs0, regs1, regs2, rpc;
22         wire [31:0] op1_res, cpsr;
23
24         /* shifter stuff */
25         wire [31:0] shift_oper;
26         wire [31:0] shift_res;
27         wire shift_cflag_out;
28
29         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
30         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
31         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
32
33         IHATEARMSHIFT blowme(.insn(insn),
34                              .operand(regs1),
35                              .reg_amt(regs2),
36                              .cflag_in(incpsr[`CPSR_C]),
37                              .res(shift_res),
38                              .cflag_out(shift_cflag_out));
39         
40         always @(*)
41                 casez (insn)
42                 32'b????000000??????????????1001????,   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
43 //              32'b????00001???????????????1001????,   /* Multiply long */
44                 32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
45                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
46                 32'b????00?10?1010001111????????????,   /* MSR (Transfer register or immediate to PSR, flag bits only) */
47                 32'b????00010?00????????00001001????,   /* Atomic swap */
48                 32'b????000100101111111111110001????,   /* Branch and exchange */
49                 32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
50                 32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
51                 32'b????011????????????????????1????,   /* Undefined. I hate ARM */
52                 32'b????01??????????????????????????,   /* Single data transfer */
53                 32'b????100?????????????????????????,   /* Block data transfer */
54                 32'b????101?????????????????????????,   /* Branch */
55                 32'b????110?????????????????????????,   /* Coprocessor data transfer */
56                 32'b????1110???????????????????0????,   /* Coprocessor data op */
57                 32'b????1110???????????????????1????,   /* Coprocessor register transfer */
58                 32'b????1111????????????????????????:   /* SWI */
59                         rpc = inpc - 8;
60                 32'b????00??????????????????????????:   /* ALU */
61                         rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
62                 default:                                /* X everything else out */
63                         rpc = 32'hxxxxxxxx;
64                 endcase
65
66         always @(*) begin
67                 read_0 = 4'hx;
68                 read_1 = 4'hx;
69                 read_2 = 4'hx;
70                 
71                 casez (insn)
72                 32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
73                 begin
74                         read_0 = insn[15:12]; /* Rn */
75                         read_1 = insn[3:0];   /* Rm */
76                         read_2 = insn[11:8];  /* Rs */
77                 end
78 //              32'b????00001???????????????1001????,   /* Multiply long */
79 //                      read_0 = insn[11:8]; /* Rn */
80 //                      read_1 = insn[3:0];   /* Rm */
81 //                      read_2 = 4'b0;       /* anyus */
82                 32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
83                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
84                 32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
85                 begin end       /* Everything stays x'ed out. */
86                 32'b????00??????????????????????????:   /* ALU */
87                 begin
88                         read_0 = insn[19:16]; /* Rn */
89                         read_1 = insn[3:0];   /* Rm */
90                         read_2 = insn[11:8];  /* Rs for shift */
91                 end
92                 32'b????00010?00????????00001001????:   /* Atomic swap */
93                 begin
94                         read_0 = insn[19:16]; /* Rn */
95                         read_1 = insn[3:0];   /* Rm */
96                 end
97                 32'b????000100101111111111110001????:   /* Branch and exchange */
98                         read_0 = insn[3:0];   /* Rn */
99                 32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
100                 begin
101                         read_0 = insn[19:16];
102                         read_1 = insn[3:0];
103                 end
104                 32'b????000??1??????????00001??1????:   /* Halfword transfer - immediate offset */
105                 begin
106                         read_0 = insn[19:16];
107                         read_1 = insn[3:0];
108                 end
109                 32'b????011????????????????????1????:   /* Undefined. I hate ARM */
110                 begin end
111                 32'b????01??????????????????????????:   /* Single data transfer */
112                 begin
113                         read_0 = insn[19:16]; /* Rn */
114                         read_1 = insn[3:0];   /* Rm */
115                 end
116                 32'b????100?????????????????????????:   /* Block data transfer */
117                         read_0 = insn[19:16];
118                 32'b????101?????????????????????????:   /* Branch */
119                 begin end
120                 32'b????110?????????????????????????:   /* Coprocessor data transfer */
121                         read_0 = insn[19:16];
122                 32'b????1110???????????????????0????,   /* Coprocessor data op */
123                 32'b????1110???????????????????1????,   /* Coprocessor register transfer */
124                 32'b????1111????????????????????????:   /* SWI */
125                 begin end
126                 default:
127                         $display("Undecoded instruction");
128                 endcase
129         end
130         
131         always @(*) begin
132                 op1_res = 32'hxxxxxxxx;
133                 cpsr = 32'hxxxxxxxx;
134                 casez (insn)
135                 32'b????000000??????????????1001????: begin /* Multiply */
136                         op1_res = regs1;
137                         cpsr = incpsr;
138                 end
139 //              32'b????00001???????????????1001????: begin /* Multiply long */
140 //                      op1_res = regs1;
141 //              end
142                 32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
143                         cpsr = incpsr;
144                 end
145                 32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
146                         cpsr = incpsr;
147                 end
148                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
149                         cpsr = incpsr;
150                 end
151                 32'b????00??????????????????????????: begin /* ALU */
152                         if(insn[25]) begin     /* the constant case */
153                                 cpsr = incpsr;
154                                 op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
155                         end else begin
156                                 cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
157                                 op1_res = shift_res;
158                         end
159                 end
160                 32'b????00010?00????????00001001????: begin /* Atomic swap */
161                         op1_res = regs1;
162                 end
163                 32'b????000100101111111111110001????: begin /* Branch and exchange */
164                         cpsr = incpsr;
165                 end
166                 32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
167                         op1_res = regs1;
168                         cpsr = incpsr;
169                 end
170                 32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
171                         op1_res = {24'b0, insn[11:8], insn[3:0]};
172                         cpsr = incpsr;
173                 end
174                 32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
175                         /* eat shit */
176                 end
177                 32'b????01??????????????????????????: begin /* Single data transfer */
178                         if(insn[25]) begin
179                                 op1_res = {20'b0, insn[11:0]};
180                                 cpsr = incpsr;
181                         end else begin
182                                 op1_res = shift_res;
183                                 cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
184                         end
185                 end
186                 32'b????100?????????????????????????: begin /* Block data transfer */
187                         op1_res = {16'b0, insn[15:0]};
188                         cpsr = incpsr;
189                 end
190                 32'b????101?????????????????????????: begin /* Branch */
191                         op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};
192                         cpsr = incpsr;
193                 end
194                 32'b????110?????????????????????????: begin /* Coprocessor data transfer */
195                         op1_res = {24'b0, insn[7:0]};
196                         cpsr = incpsr;
197                 end
198                 32'b????1110???????????????????0????: begin /* Coprocessor data op */
199                         cpsr = incpsr;
200                 end
201                 32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
202                         cpsr = incpsr;
203                 end
204                 32'b????1111????????????????????????: begin /* SWI */
205                         cpsr = incpsr;
206                 end
207                 default: begin end
208                 endcase
209         end
210
211         always @ (posedge clk) begin
212                 op0 <= regs0;   /* Rn - always */
213                 op1 <= op1_res; /* 'operand 2' - Rm */
214                 op2 <= regs2;   /* thirdedge - Rs */
215                 outcpsr <= cpsr;
216         end
217
218 endmodule
219
220 module IHATEARMSHIFT(
221         input [31:0] insn,
222         input [31:0] operand,
223         input [31:0] reg_amt,
224         input cflag_in,
225         output [31:0] res,
226         output cflag_out
227 );
228         wire [5:0] shift_amt;
229         wire elanus;
230
231
232         /* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */
233         always @(*)
234                 if(insn[4]) begin
235                         shift_amt = {|reg_amt[7:5], reg_amt[4:0]};
236                         elanus = 1'b1;
237                 end else begin
238                         shift_amt = {insn[11:7] == 5'b0, insn[11:7]};
239                         elanus = 1'b0;
240                 end
241         
242         always @(*)
243                 case (insn[6:5]) /* shift type */
244                 `SHIFT_LSL: begin
245                         {cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]};
246                 end
247                 `SHIFT_LSR: begin
248                         {res, cflag_out} = {operand, cflag_in} >> shift_amt;
249                 end
250                 `SHIFT_ASR: begin
251                         {res, cflag_out} = {operand, cflag_in} >> shift_amt | (operand[31] ? ~(33'h1FFFFFFFF >> shift_amt) : 33'b0);
252                 end
253                 `SHIFT_ROR: begin
254                         if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
255                                 res = {cflag_in, operand[31:1]};
256                                 cflag_out = operand[0];
257                         end else if(shift_amt == 6'b0) begin
258                                 res = operand;
259                                 cflag_out = cflag_in;
260                         end else begin
261                                 res = operand >> shift_amt[4:0] | operand << (5'b0 - shift_amt[4:0]);
262                                 cflag_out = operand[shift_amt[4:0] - 5'b1];
263                         end
264                 end
265                 endcase
266 endmodule
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