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a55fc9f4 JW |
1 | module MulDivDCM(input xtal, output clk); |
2 | parameter div = 5; | |
3 | parameter mul = 2; | |
4 | ||
5 | wire CLKFX_BUF; | |
6 | wire GND_BIT = 0; | |
7 | BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), | |
8 | .O(clk)); | |
9 | DCM_SP DCM_SP_INST (.CLKFB(GND_BIT), | |
10 | .CLKIN(xtal), | |
11 | .DSSEN(GND_BIT), | |
12 | .PSCLK(GND_BIT), | |
13 | .PSEN(GND_BIT), | |
14 | .PSINCDEC(GND_BIT), | |
15 | .RST(GND_BIT), | |
16 | .CLKFX(CLKFX_BUF)); | |
17 | defparam DCM_SP_INST.CLK_FEEDBACK = "NONE"; | |
18 | defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0; | |
19 | defparam DCM_SP_INST.CLKFX_DIVIDE = div; | |
20 | defparam DCM_SP_INST.CLKFX_MULTIPLY = mul; | |
21 | defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; | |
22 | defparam DCM_SP_INST.CLKIN_PERIOD = 20.000; | |
23 | defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE"; | |
24 | defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; | |
25 | defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW"; | |
26 | defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW"; | |
27 | defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE"; | |
28 | defparam DCM_SP_INST.FACTORY_JF = 16'hC080; | |
29 | defparam DCM_SP_INST.PHASE_SHIFT = 0; | |
30 | defparam DCM_SP_INST.STARTUP_WAIT = "TRUE"; | |
31 | endmodule | |
32 | ||
33 | module VTerm( | |
34 | input xtal, | |
35 | output wire vs, hs, | |
36 | output reg [2:0] red, | |
37 | output reg [2:0] green, | |
38 | output reg [1:0] blue | |
39 | ); | |
40 | ||
41 | wire clk25; | |
42 | ||
43 | wire [11:0] x, y; | |
44 | wire border; | |
45 | ||
46 | MulDivDCM dcm25(xtal, clk25); | |
47 | defparam dcm25.div = 4; | |
48 | defparam dcm25.mul = 2; | |
49 | ||
50 | SyncGen sync(clk25, vs, hs, x, y, border); | |
51 | ||
d3ae999b JW |
52 | wire [7:0] cschar; |
53 | wire [2:0] csrow; | |
54 | wire [7:0] csdata; | |
55 | ||
56 | wire [11:0] vraddr; | |
57 | wire [7:0] vrdata; | |
58 | ||
59 | reg [11:0] vwaddr = 0; | |
60 | ||
61 | wire odata; | |
62 | ||
63 | CharSet cs(cschar, csrow, csdata); | |
64 | VideoRAM vram(clk25, vraddr, vrdata, vwaddr, 8'h41, 1); | |
65 | VDisplay dpy(clk25, x, y, vraddr, vrdata, cschar, csrow, csdata, odata); | |
66 | ||
67 | always @(posedge clk25) | |
68 | vwaddr <= vwaddr + 1; | |
69 | ||
a55fc9f4 | 70 | always @(posedge clk25) begin |
d3ae999b JW |
71 | red <= border ? 0 : {3{odata}}; |
72 | green <= border ? 0 : {3{odata}}; | |
73 | blue <= border ? 0 : {2{odata}}; | |
a55fc9f4 JW |
74 | end |
75 | endmodule | |
76 | ||
77 | module SyncGen( | |
78 | input pixclk, | |
79 | output reg vs, hs, | |
80 | output reg [11:0] x, y, | |
81 | output reg border); | |
82 | ||
83 | parameter XRES = 640; | |
84 | parameter XFPORCH = 16; | |
85 | parameter XSYNC = 96; | |
86 | parameter XBPORCH = 48; | |
87 | ||
88 | parameter YRES = 480; | |
89 | parameter YFPORCH = 10; | |
90 | parameter YSYNC = 2; | |
91 | parameter YBPORCH = 29; | |
92 | ||
93 | always @(posedge pixclk) | |
94 | begin | |
95 | if (x >= (XRES + XFPORCH + XSYNC + XBPORCH)) | |
96 | begin | |
97 | if (y >= (YRES + YFPORCH + YSYNC + YBPORCH)) | |
98 | y = 0; | |
99 | else | |
100 | y = y + 1; | |
101 | x = 0; | |
102 | end else | |
103 | x = x + 1; | |
104 | hs <= (x >= (XRES + XFPORCH)) && (x < (XRES + XFPORCH + XSYNC)); | |
105 | vs <= (y >= (YRES + YFPORCH)) && (y < (YRES + YFPORCH + YSYNC)); | |
106 | border <= (x > XRES) || (y > YRES); | |
107 | end | |
108 | endmodule | |
d3ae999b JW |
109 | |
110 | module CharSet( | |
111 | input [7:0] char, | |
112 | input [2:0] row, | |
113 | output wire [7:0] data); | |
114 | ||
115 | reg [7:0] rom [(256 * 8 - 1):0]; | |
116 | ||
117 | initial | |
118 | $readmemb("ibmpc1.mem", rom); | |
119 | ||
120 | assign data = rom[{char, row}]; | |
121 | endmodule | |
122 | ||
123 | module VideoRAM( | |
124 | input pixclk, | |
125 | input [11:0] raddr, | |
126 | output reg [7:0] rdata, | |
127 | input [11:0] waddr, | |
128 | input [7:0] wdata, | |
129 | input wr); | |
130 | ||
131 | reg [7:0] ram [80*25-1 : 0]; | |
132 | ||
133 | always @(posedge pixclk) | |
134 | rdata <= ram[raddr]; | |
135 | ||
136 | always @(posedge pixclk) | |
137 | if (wr) | |
138 | ram[waddr] <= wdata; | |
139 | endmodule | |
140 | ||
141 | module VDisplay( | |
142 | input pixclk, | |
143 | input [11:0] x, | |
144 | input [11:0] y, | |
145 | output wire [11:0] raddr, | |
146 | input [7:0] rchar, | |
147 | output wire [7:0] cschar, | |
148 | output wire [2:0] csrow, | |
149 | input [7:0] csdata, | |
150 | output reg data | |
151 | ); | |
152 | ||
153 | wire [7:0] col = x[11:3]; | |
154 | wire [5:0] row = y[9:3]; | |
155 | reg [7:0] ch; | |
156 | reg [11:0] xdly; | |
157 | ||
158 | assign raddr = ({row,4'b0} + {row,6'b0} + {4'h0,col}); | |
159 | assign cschar = rchar; | |
160 | assign csrow = y[2:0]; | |
161 | ||
162 | always @(posedge pixclk) | |
163 | xdly <= x; | |
164 | ||
165 | always @(posedge pixclk) | |
166 | data = ((xdly < 80 * 8) && (y < 25 * 8)) ? csdata[7 - xdly[2:0]] : 0; | |
167 | endmodule |