[vterm.git] / VTerm.v

module MulDivDCM(input xtal, output clk);
	parameter div = 5;
	parameter mul = 2;
	
	wire CLKFX_BUF;
	wire GND_BIT = 0;
	BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
				.O(clk));
	DCM_SP DCM_SP_INST (.CLKFB(GND_BIT), 
			.CLKIN(xtal), 
			.DSSEN(GND_BIT), 
			.PSCLK(GND_BIT), 
			.PSEN(GND_BIT), 
			.PSINCDEC(GND_BIT), 
			.RST(GND_BIT), 
			.CLKFX(CLKFX_BUF));
	defparam DCM_SP_INST.CLK_FEEDBACK = "NONE";
	defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
	defparam DCM_SP_INST.CLKFX_DIVIDE = div;
	defparam DCM_SP_INST.CLKFX_MULTIPLY = mul;
	defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
	defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;
	defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
	defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
	defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
	defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
	defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
	defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
	defparam DCM_SP_INST.PHASE_SHIFT = 0;
	defparam DCM_SP_INST.STARTUP_WAIT = "TRUE";
endmodule

module VTerm(
	input xtal,
	output wire vs, hs,
	output reg [2:0] red,
	output reg [2:0] green,
	output reg [1:0] blue
	);
	
	wire clk25;

	wire [11:0] x, y;
	wire border;

	MulDivDCM dcm25(xtal, clk25);
	defparam dcm25.div = 4;
	defparam dcm25.mul = 2;

	SyncGen sync(clk25, vs, hs, x, y, border);
	
	always @(posedge clk25) begin
		red <= border ? 0 : 3'b100;
		green <= border ? 0 : 0;
		blue <= border ? 0 : 0;
	end
endmodule

module SyncGen(
	input pixclk,
	output reg vs, hs,
	output reg [11:0] x, y,
	output reg border);
	
	parameter XRES = 640;
	parameter XFPORCH = 16;
	parameter XSYNC = 96;
	parameter XBPORCH = 48;
	
	parameter YRES = 480;
	parameter YFPORCH = 10;
	parameter YSYNC = 2;
	parameter YBPORCH = 29;
	
	always @(posedge pixclk)
	begin
		if (x >= (XRES + XFPORCH + XSYNC + XBPORCH))
		begin
			if (y >= (YRES + YFPORCH + YSYNC + YBPORCH))
				y = 0;
			else
				y = y + 1;
			x = 0;
		end else
			x = x + 1;
		hs <= (x >= (XRES + XFPORCH)) && (x < (XRES + XFPORCH + XSYNC));
		vs <= (y >= (YRES + YFPORCH)) && (y < (YRES + YFPORCH + YSYNC));
		border <= (x > XRES) || (y > YRES);
	end
endmodule
Commit	Line	Data
a55fc9f4 JW	1	module MulDivDCM(input xtal, output clk);
	2	parameter div = 5;
	3	parameter mul = 2;
	4
	5	wire CLKFX_BUF;
	6	wire GND_BIT = 0;
	7	BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
	8	.O(clk));
	9	DCM_SP DCM_SP_INST (.CLKFB(GND_BIT),
	10	.CLKIN(xtal),
	11	.DSSEN(GND_BIT),
	12	.PSCLK(GND_BIT),
	13	.PSEN(GND_BIT),
	14	.PSINCDEC(GND_BIT),
	15	.RST(GND_BIT),
	16	.CLKFX(CLKFX_BUF));
	17	defparam DCM_SP_INST.CLK_FEEDBACK = "NONE";
	18	defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
	19	defparam DCM_SP_INST.CLKFX_DIVIDE = div;
	20	defparam DCM_SP_INST.CLKFX_MULTIPLY = mul;
	21	defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
	22	defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;
	23	defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
	24	defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
	25	defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
	26	defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
	27	defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
	28	defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
	29	defparam DCM_SP_INST.PHASE_SHIFT = 0;
	30	defparam DCM_SP_INST.STARTUP_WAIT = "TRUE";
	31	endmodule
	32
	33	module VTerm(
	34	input xtal,
	35	output wire vs, hs,
	36	output reg [2:0] red,
	37	output reg [2:0] green,
	38	output reg [1:0] blue
	39	);
	40
	41	wire clk25;
	42
	43	wire [11:0] x, y;
	44	wire border;
	45
	46	MulDivDCM dcm25(xtal, clk25);
	47	defparam dcm25.div = 4;
	48	defparam dcm25.mul = 2;
	49
	50	SyncGen sync(clk25, vs, hs, x, y, border);
	51
	52	always @(posedge clk25) begin
	53	red <= border ? 0 : 3'b100;
	54	green <= border ? 0 : 0;
	55	blue <= border ? 0 : 0;
	56	end
	57	endmodule
	58
	59	module SyncGen(
	60	input pixclk,
	61	output reg vs, hs,
	62	output reg [11:0] x, y,
	63	output reg border);
	64
65	parameter XRES = 640;
66	parameter XFPORCH = 16;
67	parameter XSYNC = 96;
68	parameter XBPORCH = 48;
69
70	parameter YRES = 480;
71	parameter YFPORCH = 10;
72	parameter YSYNC = 2;
73	parameter YBPORCH = 29;
74
75	always @(posedge pixclk)
76	begin
77	if (x >= (XRES + XFPORCH + XSYNC + XBPORCH))
78	begin
79	if (y >= (YRES + YFPORCH + YSYNC + YBPORCH))
80	y = 0;
81	else
82	y = y + 1;
83	x = 0;
84	end else
85	x = x + 1;
86	hs <= (x >= (XRES + XFPORCH)) && (x < (XRES + XFPORCH + XSYNC));
87	vs <= (y >= (YRES + YFPORCH)) && (y < (YRES + YFPORCH + YSYNC));
88	border <= (x > XRES) \|\| (y > YRES);
89	end
90	endmodule