ich2/smi.c

   1 #include <smi.h>
   2 #include <pci.h>
   3 #include <io.h>
   4 #include <stdint.h>
   5 #include <vga-overlay.h>
   6 #include <reg-82801b.h>
   7 #include <output.h>
   8
   9 static smi_handler_t _handlers[SMI_EVENT_MAX] = {0};
  10
  11 static uint16_t _get_PMBASE()
  12 {
  13         static long pmbase = -1;
  14
  15         if (pmbase == -1)       /* Memoize it so that we don't have to hit PCI so often. */
  16                 pmbase = pci_read32(ICH2_LPC_BUS, ICH2_LPC_DEV, ICH2_LPC_FN, ICH2_LPC_PCI_PMBASE) & ICH2_PMBASE_MASK;
  17
  18         return pmbase;
  19 }
  20
  21 void smi_disable()
  22 {
  23         unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
  24         outl(smi_en, inl(smi_en) & ~ICH2_SMI_EN_GBL_SMI_EN);
  25 }
  26
  27 void smi_enable()
  28 {
  29         unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
  30         outl(smi_en, inl(smi_en) | ICH2_SMI_EN_GBL_SMI_EN);
  31 }
  32
  33 unsigned long smi_status()
  34 {
  35         unsigned short smi_sts = _get_PMBASE() + ICH2_PMBASE_SMI_STS;
  36         return inl(smi_sts);
  37 }
  38
  39 void smi_poll()
  40 {
  41         unsigned long sts = smi_status();
  42
  43         if (sts & ICH2_SMI_STS_BIOS_STS)
  44         {
  45                 if (_handlers[SMI_EVENT_GBL_RLS] == SMI_HANDLER_NONE)
  46                         output("Unhandled: BIOS_STS");
  47                 else if (_handlers[SMI_EVENT_GBL_RLS] != SMI_HANDLER_IGNORE)
  48                         _handlers[SMI_EVENT_GBL_RLS](SMI_EVENT_GBL_RLS);
  49                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
  50         }
  51
  52         if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
  53         {
  54                 output("Unhandled: LEGACY_USB_STS");
  55                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
  56         }
  57
  58         if (sts & ICH2_SMI_STS_SLP_SMI_STS)
  59         {
  60                 output("Unhandled: SLP_SMI_STS");
  61                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
  62         }
  63
  64         if (sts & ICH2_SMI_STS_APM_STS)
  65         {
  66                 output("Unhandled: APM_STS");
  67                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_APM_STS);
  68         }
  69
  70         if (sts & ICH2_SMI_STS_SWSMI_TMR_STS)   // Ack it, then request another.
  71         {
  72                 if (_handlers[SMI_EVENT_FAST_TIMER] == SMI_HANDLER_NONE)
  73                         output("Unhandled: SWSMI_TMR_STS");
  74                 else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
  75                         _handlers[SMI_EVENT_FAST_TIMER](SMI_EVENT_FAST_TIMER);
  76                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SWSMI_TMR_STS);
  77         }
  78
  79         if (sts & ICH2_SMI_STS_PM1_STS_REG)
  80         {
  81                 unsigned short pm1_sts = inw(_get_PMBASE() + ICH2_PMBASE_PM1_STS);
  82                 unsigned short pm1_en = inw(_get_PMBASE() + ICH2_PMBASE_PM1_EN);
  83
  84                 pm1_sts &= pm1_en;
  85                 if (pm1_sts & ICH2_PM1_STS_RTC_STS)
  86                 {
  87                         output("Unhandled: PM1_STS: RTC_STS");
  88                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
  89                 }
  90
  91                 if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
  92                 {
  93                         output("Unhandled: PM1_STS: PWRBTN_STS");
  94                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
  95                 }
  96
  97                 if (pm1_sts & ICH2_PM1_STS_GBL_STS)
  98                 {
  99                         output("Unhandled: PM1_STS: GBL_STS");
 100                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
 101                 }
 102
 103                 if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
 104                 {
 105                         output("Unhandled: PM1_STS: TMROF_STS");
 106                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_TMROF_STS);
 107                 }
 108
 109                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PM1_STS_REG);
 110         }
 111
 112         if (sts & ICH2_SMI_STS_GPE0_STS)
 113         {
 114                 /* XXX -- trawl through GPE0_STS to see what happened */
 115                 output("XXX Unhandled: GPE0_STS (expect lockup)");
 116         }
 117
 118         if (sts & ICH2_SMI_STS_GPE1_STS)
 119         {
 120                 /* XXX -- trawl through GPE1_STS to see what happened */
 121                 output("XXX Unhandled: GPE1_STS (expect lockup)");
 122         }
 123
 124         if (sts & ICH2_SMI_STS_MCSMI_STS)
 125         {
 126                 output("Unhandled: MCSMI_STS");
 127                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_MCSMI_STS);
 128         }
 129
 130         if (sts & ICH2_SMI_STS_DEVMON_STS)
 131         {
 132                 unsigned short mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
 133                 unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
 134                 unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
 135
 136                 if (devact_sts & ICH2_DEVACT_STS_KBC_ACT_STS)
 137                 {
 138                         if (_handlers[SMI_EVENT_DEVTRAP_KBC] == SMI_HANDLER_NONE)
 139                                 output("Unhandled: DEVACT_KBC_ACT_STS");
 140                         else if (_handlers[SMI_EVENT_DEVTRAP_KBC] != SMI_HANDLER_IGNORE)
 141                                 _handlers[SMI_EVENT_DEVTRAP_KBC](SMI_EVENT_DEVTRAP_KBC);
 142                         outl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS, ICH2_DEVACT_STS_KBC_ACT_STS);
 143                 }
 144
 145                 /* Refresh register cache so that we can print unhandleds as needed. */
 146                 mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
 147                 devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
 148                 devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
 149
 150                 if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
 151                         outputf("Unhandled: MON_SMI (%04x)", mon_smi);
 152                 if (devact_sts & devtrap_en)
 153                         outputf("Unhandled: DEVTRAP (%08x)", devact_sts & devtrap_en);
 154         }
 155
 156         if (sts & ICH2_SMI_STS_TCO_STS)
 157         {
 158                 output("Unhandled: TCO_STS");
 159                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
 160         }
 161
 162         if (sts & ICH2_SMI_STS_PERIODIC_STS)
 163         {
 164                 output("Unhandled: PERIODIC_STS");
 165                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
 166         }
 167
 168         if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
 169         {
 170                 output("Unhandled: SERIRQ_SMI_STS");
 171                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
 172         }
 173
 174         if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
 175         {
 176                 output("Unhandled: SMBUS_SMI_STS");
 177                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
 178         }
 179
 180         if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG)   /* Either the chipset is buggy, or we are. */
 181                 outputf("WARN: couldn't clear SMI_STS! (%08x)", smi_status());
 182
 183         outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 184                 inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 185                         ICH2_SMI_EN_EOS |
 186                         ICH2_SMI_EN_GBL_SMI_EN);
 187 }
 188
 189 int smi_register_handler(smi_event_t ev, smi_handler_t hnd)
 190 {
 191         if (ev >= SMI_EVENT_MAX)
 192                 return -1;
 193         _handlers[ev] = hnd;
 194         return 0;
 195 }
 196
 197 int smi_enable_event(smi_event_t ev)
 198 {
 199         switch(ev)
 200         {
 201         case SMI_EVENT_FAST_TIMER:
 202                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 203                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 204                                 ICH2_SMI_EN_SWSMI_TMR_EN);
 205                 return 0;
 206         case SMI_EVENT_DEVTRAP_KBC:
 207                 outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
 208                         inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) |
 209                                 ICH2_DEVTRAP_EN_KBC_TRP_EN);
 210                 return 0;
 211         case SMI_EVENT_GBL_RLS:
 212                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 213                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 214                                 ICH2_SMI_EN_BIOS_EN);
 215                 return 0;
 216         default:
 217                 return -1;
 218         }
 219 }
 220
 221 int smi_disable_event(smi_event_t ev)
 222 {
 223         switch(ev)
 224         {
 225         case SMI_EVENT_FAST_TIMER:
 226                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 227                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
 228                                 ~ICH2_SMI_EN_SWSMI_TMR_EN);
 229                 return 0;
 230         case SMI_EVENT_DEVTRAP_KBC:
 231                 outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
 232                         inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
 233                                 ~ICH2_DEVTRAP_EN_KBC_TRP_EN);
 234                 return 0;
 235         case SMI_EVENT_GBL_RLS:
 236                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 237                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
 238                                 ~ICH2_SMI_EN_BIOS_EN);
 239                 return 0;
 240         default:
 241                 return -1;
 242         }
 243 }