git.joshuawise.com / netwatch.git / blame
| Commit | Line | Data |
|---|---|---|
| 3c4e084d JP |
1 | /* reg-82801b.h |
| 2 | * Register macros for Intel 82801B | |
| 3 | * NetWatch system management mode administration console | |
| 4 | * | |
| 5 | * Copyright (c) 2008 Jacob Potter and Joshua Wise. All rights reserved. | |
| 6 | * This program is free software; you can redistribute and/or modify it under | |
| 7 | * the terms found in the file LICENSE in the root of this source tree. | |
| 8 | * | |
| 9 | */ | |
| 10 | ||
| cc80dccf JW |
11 | #ifndef _REG_82801B_H |
| 12 | #define _REG_82801B_H | |
| 13 | ||
| 14 | #define ICH2_PCI_BRIDGE_BUS 0 | |
| 15 | #define ICH2_PCI_BRIDGE_DEV 30 | |
| 16 | #define ICH2_PCI_BRIDGE_FN 0 | |
| 17 | ||
| 18 | #define ICH2_NIC_BUS 1 | |
| 19 | #define ICH2_NIC_DEV 8 | |
| 20 | #define ICH2_NIC_FN 0 | |
| 21 | ||
| 22 | #define ICH2_LPC_BUS 0 | |
| 23 | #define ICH2_LPC_DEV 31 | |
| 24 | #define ICH2_LPC_FN 0 | |
| 25 | ||
| 26 | #define ICH2_LPC_PCI_PMBASE 0x40 | |
| 27 | #define ICH2_PMBASE_MASK 0xFF80 | |
| 28 | #define ICH2_LPC_PCI_ACPI_CTRL 0x44 | |
| 29 | #define ICH2_LPC_PCI_GPIOBASE 0x58 | |
| 30 | #define ICH2_LPC_PCI_GPIO_CNTL 0x5C | |
| 31 | #define ICH2_LPC_PCI_GEN_PMCON1 0xA0 | |
| 32 | #define ICH2_LPC_PCI_GEN_PMCON2 0xA2 | |
| 33 | #define ICH2_LPC_PCI_GEN_PMCON3 0xA4 | |
| 34 | #define ICH2_LPC_PCI_GPI_ROUT 0xB8 | |
| 35 | #define ICH2_LPC_PCI_TRP_FWD_EN 0xC0 | |
| 36 | #define ICH2_LPC_PCI_MON4_TRP_RNG 0xC4 | |
| 37 | #define ICH2_LPC_PCI_MON5_TRP_RNG 0xC6 | |
| 38 | #define ICH2_LPC_PCI_MON6_TRP_RNG 0xC8 | |
| 39 | #define ICH2_LPC_PCI_MON7_TRP_RNG 0xCA | |
| 40 | #define ICH2_LPC_PCI_MON_TRP_MSK 0xCC | |
| 41 | ||
| 199c2b1b JW |
42 | #define ICH2_PMBASE_PM1_STS 0x00 |
| 43 | #define ICH2_PM1_STS_WAK_STS (1 << 15) | |
| 44 | #define ICH2_PM1_STS_PRBTNOR_STS (1 << 11) | |
| 45 | #define ICH2_PM1_STS_RTC_STS (1 << 10) | |
| 46 | #define ICH2_PM1_STS_PWRBTN_STS (1 << 8) | |
| 47 | #define ICH2_PM1_STS_GBL_STS (1 << 5) | |
| 48 | #define ICH2_PM1_STS_BM_STS (1 << 4) | |
| 49 | #define ICH2_PM1_STS_TMROF_STS (1 << 0) | |
| 50 | ||
| 51 | #define ICH2_PMBASE_PM1_EN 0x02 | |
| 52 | #define ICH2_PM1_EN_RTC_EN (1 << 10) | |
| 53 | #define ICH2_PM1_EN_PWRBTN_EN (1 << 8) | |
| 54 | #define ICH2_PM1_EN_GBL_EN (1 << 5) | |
| 55 | #define ICH2_PM1_EN_TMROF_EN (1 << 0 | |
| 56 | ||
| 20ef1208 JW |
57 | #define ICH2_PMBASE_PM1_TMR 0x08 |
| 58 | #define ICH2_PM1_TMR_FREQ 3579545 /* This will be the encryption key for a question on the test. */ | |
| 59 | ||
| cc80dccf JW |
60 | #define ICH2_PMBASE_SMI_EN 0x30 |
| 61 | #define ICH2_SMI_EN_PERIODIC_EN (1 << 14) | |
| 62 | #define ICH2_SMI_EN_TCO_EN (1 << 13) | |
| 63 | #define ICH2_SMI_EN_MCSMI_EN (1 << 11) | |
| 64 | #define ICH2_SMI_EN_BIOS_RLS (1 << 7) | |
| 65 | #define ICH2_SMI_EN_SWSMI_TMR_EN (1 << 6) | |
| 66 | #define ICH2_SMI_EN_APMC_EN (1 << 5) | |
| 67 | #define ICH2_SMI_EN_SLP_SMI_EN (1 << 4) | |
| 68 | #define ICH2_SMI_EN_LEGACY_USB_EN (1 << 3) | |
| 69 | #define ICH2_SMI_EN_BIOS_EN (1 << 2) | |
| 70 | #define ICH2_SMI_EN_EOS (1 << 1) | |
| 71 | #define ICH2_SMI_EN_GBL_SMI_EN (1 << 0) | |
| 72 | ||
| 73 | #define ICH2_PMBASE_SMI_STS 0x34 | |
| 74 | #define ICH2_SMI_STS_SMBUS_SMI_STS (1 << 16) | |
| 75 | #define ICH2_SMI_STS_SERIRQ_SMI_STS (1 << 15) | |
| 76 | #define ICH2_SMI_STS_PERIODIC_STS (1 << 14) | |
| 77 | #define ICH2_SMI_STS_TCO_STS (1 << 13) | |
| 78 | #define ICH2_SMI_STS_DEVMON_STS (1 << 12) | |
| 79 | #define ICH2_SMI_STS_MCSMI_STS (1 << 11) | |
| 80 | #define ICH2_SMI_STS_GPE1_STS (1 << 10) | |
| 81 | #define ICH2_SMI_STS_GPE0_STS (1 << 9) | |
| 82 | #define ICH2_SMI_STS_PM1_STS_REG (1 << 8) | |
| 83 | #define ICH2_SMI_STS_SWSMI_TMR_STS (1 << 6) | |
| 84 | #define ICH2_SMI_STS_APM_STS (1 << 5) | |
| 85 | #define ICH2_SMI_STS_SLP_SMI_STS (1 << 4) | |
| 86 | #define ICH2_SMI_STS_LEGACY_USB_STS (1 << 3) | |
| 87 | #define ICH2_SMI_STS_BIOS_STS (1 << 2) | |
| 88 | ||
| 4fb81ad0 JW |
89 | #define ICH2_PMBASE_MON_SMI 0x40 |
| 90 | #define ICH2_MON_SMI_DEV7_TRAP_STS (1 << 15) | |
| 91 | #define ICH2_MON_SMI_DEV6_TRAP_STS (1 << 14) | |
| 92 | #define ICH2_MON_SMI_DEV5_TRAP_STS (1 << 13) | |
| 93 | #define ICH2_MON_SMI_DEV4_TRAP_STS (1 << 12) | |
| 94 | #define ICH2_MON_SMI_DEV7_TRAP_EN (1 << 11) | |
| 95 | #define ICH2_MON_SMI_DEV6_TRAP_EN (1 << 10) | |
| 96 | #define ICH2_MON_SMI_DEV5_TRAP_EN (1 << 9) | |
| 97 | #define ICH2_MON_SMI_DEV4_TRAP_EN (1 << 8) | |
| 98 | ||
| 99 | #define ICH2_PMBASE_DEVACT_STS 0x44 | |
| 100 | #define ICH2_DEVACT_STS_ADLIB_ACT_STS (1 << 13) | |
| 101 | #define ICH2_DEVACT_STS_KBC_ACT_STS (1 << 12) | |
| 102 | #define ICH2_DEVACT_STS_MIDI_ACT_STS (1 << 11) | |
| 103 | #define ICH2_DEVACT_STS_AUDIO_ACT_STS (1 << 10) | |
| 104 | #define ICH2_DEVACT_STS_PIRQDH_ACT_STS (1 << 9) | |
| 105 | #define ICH2_DEVACT_STS_PIRQCG_ACT_STS (1 << 8) | |
| 106 | #define ICH2_DEVACT_STS_PIRQBF_ACT_STS (1 << 7) | |
| 107 | #define ICH2_DEVACT_STS_PIRQAE_ACT_STS (1 << 6) | |
| 108 | #define ICH2_DEVACT_STS_LEG_ACT_STS (1 << 5) | |
| 109 | #define ICH2_DEVACT_STS_IDES1_ACT_STS (1 << 3) | |
| 110 | #define ICH2_DEVACT_STS_IDES0_ACT_STS (1 << 2) | |
| 111 | #define ICH2_DEVACT_STS_IDEP1_ACT_STS (1 << 1) | |
| 112 | #define ICH2_DEVACT_STS_IDEP0_ACT_STS (1 << 0) | |
| 113 | ||
| 114 | #define ICH2_PMBASE_DEVTRAP_EN 0x48 | |
| 115 | #define ICH2_DEVTRAP_EN_ADLIB_TRP_EN (1 << 13) | |
| 116 | #define ICH2_DEVTRAP_EN_KBC_TRP_EN (1 << 12) | |
| 117 | #define ICH2_DEVTRAP_EN_MIDI_TRP_EN (1 << 11) | |
| 118 | #define ICH2_DEVTRAP_EN_AUDIO_TRP_EN (1 << 10) | |
| 119 | #define ICH2_DEVTRAP_EN_LEG_TRP_EN (1 << 5) | |
| 120 | #define ICH2_DEVTRAP_EN_IDES1_TRP_EN (1 << 3) | |
| 121 | #define ICH2_DEVTRAP_EN_IDES0_TRP_EN (1 << 2) | |
| 122 | #define ICH2_DEVTRAP_EN_IDEP1_TRP_EN (1 << 1) | |
| 123 | #define ICH2_DEVTRAP_EN_IDEP0_TRP_EN (1 << 0) | |
| 124 | ||
| cc80dccf JW |
125 | #define ICH2_IDE_BUS 0 |
| 126 | #define ICH2_IDE_DEV 31 | |
| 127 | #define ICH2_IDE_FN 1 | |
| 128 | ||
| 129 | #define ICH2_USB0_BUS 0 | |
| 130 | #define ICH2_USB0_DEV 31 | |
| 131 | #define ICH2_USB0_FN 2 | |
| 132 | ||
| 133 | #define ICH2_USB1_BUS 0 | |
| 134 | #define ICH2_USB1_DEV 31 | |
| 135 | #define ICH2_USB1_FN 4 | |
| 136 | ||
| 137 | #define ICH2_SMBUS_BUS 0 | |
| 138 | #define ICH2_SMBUS_DEV 31 | |
| 139 | #define ICH2_SMBUS_FN 3 | |
| 140 | ||
| 141 | #define ICH2_AC97AUD_BUS 0 | |
| 142 | #define ICH2_AC97AUD_DEV 31 | |
| 143 | #define ICH2_AC97AUD_FN 5 | |
| 144 | ||
| 145 | #define ICH2_AC97MOD_BUS 0 | |
| 146 | #define ICH2_AC97MOD_DEV 31 | |
| 147 | #define ICH2_AC97MOD_FN 6 | |
| 148 | ||
| 149 | #endif |