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cc80dccf JW |
1 | #ifndef _REG_82801B_H |
2 | #define _REG_82801B_H | |
3 | ||
4 | #define ICH2_PCI_BRIDGE_BUS 0 | |
5 | #define ICH2_PCI_BRIDGE_DEV 30 | |
6 | #define ICH2_PCI_BRIDGE_FN 0 | |
7 | ||
8 | #define ICH2_NIC_BUS 1 | |
9 | #define ICH2_NIC_DEV 8 | |
10 | #define ICH2_NIC_FN 0 | |
11 | ||
12 | #define ICH2_LPC_BUS 0 | |
13 | #define ICH2_LPC_DEV 31 | |
14 | #define ICH2_LPC_FN 0 | |
15 | ||
16 | #define ICH2_LPC_PCI_PMBASE 0x40 | |
17 | #define ICH2_PMBASE_MASK 0xFF80 | |
18 | #define ICH2_LPC_PCI_ACPI_CTRL 0x44 | |
19 | #define ICH2_LPC_PCI_GPIOBASE 0x58 | |
20 | #define ICH2_LPC_PCI_GPIO_CNTL 0x5C | |
21 | #define ICH2_LPC_PCI_GEN_PMCON1 0xA0 | |
22 | #define ICH2_LPC_PCI_GEN_PMCON2 0xA2 | |
23 | #define ICH2_LPC_PCI_GEN_PMCON3 0xA4 | |
24 | #define ICH2_LPC_PCI_GPI_ROUT 0xB8 | |
25 | #define ICH2_LPC_PCI_TRP_FWD_EN 0xC0 | |
26 | #define ICH2_LPC_PCI_MON4_TRP_RNG 0xC4 | |
27 | #define ICH2_LPC_PCI_MON5_TRP_RNG 0xC6 | |
28 | #define ICH2_LPC_PCI_MON6_TRP_RNG 0xC8 | |
29 | #define ICH2_LPC_PCI_MON7_TRP_RNG 0xCA | |
30 | #define ICH2_LPC_PCI_MON_TRP_MSK 0xCC | |
31 | ||
32 | #define ICH2_PMBASE_SMI_EN 0x30 | |
33 | #define ICH2_SMI_EN_PERIODIC_EN (1 << 14) | |
34 | #define ICH2_SMI_EN_TCO_EN (1 << 13) | |
35 | #define ICH2_SMI_EN_MCSMI_EN (1 << 11) | |
36 | #define ICH2_SMI_EN_BIOS_RLS (1 << 7) | |
37 | #define ICH2_SMI_EN_SWSMI_TMR_EN (1 << 6) | |
38 | #define ICH2_SMI_EN_APMC_EN (1 << 5) | |
39 | #define ICH2_SMI_EN_SLP_SMI_EN (1 << 4) | |
40 | #define ICH2_SMI_EN_LEGACY_USB_EN (1 << 3) | |
41 | #define ICH2_SMI_EN_BIOS_EN (1 << 2) | |
42 | #define ICH2_SMI_EN_EOS (1 << 1) | |
43 | #define ICH2_SMI_EN_GBL_SMI_EN (1 << 0) | |
44 | ||
45 | #define ICH2_PMBASE_SMI_STS 0x34 | |
46 | #define ICH2_SMI_STS_SMBUS_SMI_STS (1 << 16) | |
47 | #define ICH2_SMI_STS_SERIRQ_SMI_STS (1 << 15) | |
48 | #define ICH2_SMI_STS_PERIODIC_STS (1 << 14) | |
49 | #define ICH2_SMI_STS_TCO_STS (1 << 13) | |
50 | #define ICH2_SMI_STS_DEVMON_STS (1 << 12) | |
51 | #define ICH2_SMI_STS_MCSMI_STS (1 << 11) | |
52 | #define ICH2_SMI_STS_GPE1_STS (1 << 10) | |
53 | #define ICH2_SMI_STS_GPE0_STS (1 << 9) | |
54 | #define ICH2_SMI_STS_PM1_STS_REG (1 << 8) | |
55 | #define ICH2_SMI_STS_SWSMI_TMR_STS (1 << 6) | |
56 | #define ICH2_SMI_STS_APM_STS (1 << 5) | |
57 | #define ICH2_SMI_STS_SLP_SMI_STS (1 << 4) | |
58 | #define ICH2_SMI_STS_LEGACY_USB_STS (1 << 3) | |
59 | #define ICH2_SMI_STS_BIOS_STS (1 << 2) | |
60 | ||
61 | #define ICH2_IDE_BUS 0 | |
62 | #define ICH2_IDE_DEV 31 | |
63 | #define ICH2_IDE_FN 1 | |
64 | ||
65 | #define ICH2_USB0_BUS 0 | |
66 | #define ICH2_USB0_DEV 31 | |
67 | #define ICH2_USB0_FN 2 | |
68 | ||
69 | #define ICH2_USB1_BUS 0 | |
70 | #define ICH2_USB1_DEV 31 | |
71 | #define ICH2_USB1_FN 4 | |
72 | ||
73 | #define ICH2_SMBUS_BUS 0 | |
74 | #define ICH2_SMBUS_DEV 31 | |
75 | #define ICH2_SMBUS_FN 3 | |
76 | ||
77 | #define ICH2_AC97AUD_BUS 0 | |
78 | #define ICH2_AC97AUD_DEV 31 | |
79 | #define ICH2_AC97AUD_FN 5 | |
80 | ||
81 | #define ICH2_AC97MOD_BUS 0 | |
82 | #define ICH2_AC97MOD_DEV 31 | |
83 | #define ICH2_AC97MOD_FN 6 | |
84 | ||
85 | #endif |