[netwatch.git] / ich2 / smi.c

/* smi.c
 * System management interrupt dispatch routines for ICH2 southbridge
 * NetWatch system management mode administration console
 *
 * Copyright (c) 2008 Jacob Potter and Joshua Wise.  All rights reserved.
 * This program is free software; you can redistribute and/or modify it under
 * the terms found in the file LICENSE in the root of this source tree. 
 *
 */


#include <smi.h>
#include <pci.h>
#include <io.h>
#include <stdint.h>
#include <vga-overlay.h>
#include <reg-82801b.h>
#include <output.h>

static smi_handler_t _handlers[SMI_EVENT_MAX] = {0};

static uint16_t _get_PMBASE()
{
	static long pmbase = -1;
	
	if (pmbase == -1)	/* Memoize it so that we don't have to hit PCI so often. */
		pmbase = pci_read32(ICH2_LPC_BUS, ICH2_LPC_DEV, ICH2_LPC_FN, ICH2_LPC_PCI_PMBASE) & ICH2_PMBASE_MASK;
	
	return pmbase;
}

void smi_disable()
{
	unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
	outl(smi_en, inl(smi_en) & ~ICH2_SMI_EN_GBL_SMI_EN);
	
	/* Try really hard to shut up USB_LEGKEY. */
	pci_write16(ICH2_USB0_BUS, ICH2_USB0_DEV, ICH2_USB0_FN, ICH2_USB_LEGKEY, 0x0);
	pci_write16(ICH2_USB0_BUS, ICH2_USB0_DEV, ICH2_USB0_FN, ICH2_USB_LEGKEY,
		pci_read16(ICH2_USB0_BUS, ICH2_USB0_DEV, ICH2_USB0_FN, ICH2_USB_LEGKEY));
	pci_write16(ICH2_USB1_BUS, ICH2_USB1_DEV, ICH2_USB1_FN, ICH2_USB_LEGKEY, 0x0);
	pci_write16(ICH2_USB1_BUS, ICH2_USB1_DEV, ICH2_USB1_FN, ICH2_USB_LEGKEY,
		pci_read16(ICH2_USB1_BUS, ICH2_USB1_DEV, ICH2_USB1_FN, ICH2_USB_LEGKEY));
	
}

void smi_enable()
{
	unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
	outl(smi_en, inl(smi_en) | ICH2_SMI_EN_GBL_SMI_EN);
}

unsigned long smi_status()
{
	unsigned short smi_sts = _get_PMBASE() + ICH2_PMBASE_SMI_STS;
	return inl(smi_sts);
}

void smi_poll()
{
	unsigned long sts = smi_status();
	
	if (sts & ICH2_SMI_STS_BIOS_STS)
	{
		if (_handlers[SMI_EVENT_GBL_RLS] == SMI_HANDLER_NONE)
			output("Unhandled: BIOS_STS");
		else if (_handlers[SMI_EVENT_GBL_RLS] != SMI_HANDLER_IGNORE)
			_handlers[SMI_EVENT_GBL_RLS](SMI_EVENT_GBL_RLS);
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
	}
	
	if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
	{
		output("Unhandled: LEGACY_USB_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
	}
	
	if (sts & ICH2_SMI_STS_SLP_SMI_STS)
	{
		output("Unhandled: SLP_SMI_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
	}
	
	if (sts & ICH2_SMI_STS_APM_STS)
	{
		output("Unhandled: APM_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_APM_STS);
	}
	
	if (sts & ICH2_SMI_STS_SWSMI_TMR_STS)	// Ack it, then request another.
	{
		if (_handlers[SMI_EVENT_FAST_TIMER] == SMI_HANDLER_NONE)
			output("Unhandled: SWSMI_TMR_STS");
		else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
			_handlers[SMI_EVENT_FAST_TIMER](SMI_EVENT_FAST_TIMER);
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SWSMI_TMR_STS);
	}
	
	if (sts & ICH2_SMI_STS_PM1_STS_REG)
	{
		unsigned short pm1_sts = inw(_get_PMBASE() + ICH2_PMBASE_PM1_STS);
		unsigned short pm1_en = inw(_get_PMBASE() + ICH2_PMBASE_PM1_EN);
		
		pm1_sts &= pm1_en;
		if (pm1_sts & ICH2_PM1_STS_RTC_STS)
		{
			output("Unhandled: PM1_STS: RTC_STS");
			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
		}
		
		if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
		{
			if (_handlers[SMI_EVENT_PWRBTN] == SMI_HANDLER_NONE)
				output("Unhandled: PM1_STS: PWRBTN_STS");
			else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
				_handlers[SMI_EVENT_PWRBTN](SMI_EVENT_PWRBTN);
			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
		}
		
		if (pm1_sts & ICH2_PM1_STS_GBL_STS)
		{
			output("Unhandled: PM1_STS: GBL_STS");
			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
		}
		
		if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
		{
			output("Unhandled: PM1_STS: TMROF_STS");
			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_TMROF_STS);
		}
		
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PM1_STS_REG);
	}
	
	if (sts & ICH2_SMI_STS_GPE0_STS)
	{
		/* XXX -- trawl through GPE0_STS to see what happened */
		output("XXX Unhandled: GPE0_STS (expect lockup)");
	}
	
	if (sts & ICH2_SMI_STS_GPE1_STS)
	{
		/* XXX -- trawl through GPE1_STS to see what happened */
		output("XXX Unhandled: GPE1_STS (expect lockup)");
	}
	
	if (sts & ICH2_SMI_STS_MCSMI_STS)
	{
		output("Unhandled: MCSMI_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_MCSMI_STS);
	}
	
	if (sts & ICH2_SMI_STS_DEVMON_STS)
	{
		unsigned short mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
		unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
		unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
		
		if (devact_sts & ICH2_DEVACT_STS_KBC_ACT_STS)
		{
			if (_handlers[SMI_EVENT_DEVTRAP_KBC] == SMI_HANDLER_NONE)
				output("Unhandled: DEVACT_KBC_ACT_STS");
			else if (_handlers[SMI_EVENT_DEVTRAP_KBC] != SMI_HANDLER_IGNORE)
				_handlers[SMI_EVENT_DEVTRAP_KBC](SMI_EVENT_DEVTRAP_KBC);
			outl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS, ICH2_DEVACT_STS_KBC_ACT_STS);
		}
		
		/* Refresh register cache so that we can print unhandleds as needed. */
		mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
		devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
		devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
		
		if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
			outputf("Unhandled: MON_SMI (%04x)", mon_smi);
		if (devact_sts & devtrap_en)
			outputf("Unhandled: DEVTRAP (%08x)", devact_sts & devtrap_en);
	}
	
	if (sts & ICH2_SMI_STS_TCO_STS)
	{
		output("Unhandled: TCO_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
	}
	
	if (sts & ICH2_SMI_STS_PERIODIC_STS)
	{
		output("Unhandled: PERIODIC_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
	}
	
	if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
	{
		output("Unhandled: SERIRQ_SMI_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
	}
	
	if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
	{
		output("Unhandled: SMBUS_SMI_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
	}
	
	if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG)	/* Either the chipset is buggy, or we are. */
		outputf("WARN: couldn't clear SMI_STS! (%08x)", smi_status());
	
	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
		inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
			ICH2_SMI_EN_EOS |
			ICH2_SMI_EN_GBL_SMI_EN);
}

int smi_register_handler(smi_event_t ev, smi_handler_t hnd)
{
	if (ev >= SMI_EVENT_MAX)
		return -1;
	_handlers[ev] = hnd;
	return 0;
}

int smi_enable_event(smi_event_t ev)
{
	switch(ev)
	{
	case SMI_EVENT_FAST_TIMER:
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
				ICH2_SMI_EN_SWSMI_TMR_EN);
		return 0;
	case SMI_EVENT_DEVTRAP_KBC:
		outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) |
				ICH2_DEVTRAP_EN_KBC_TRP_EN);
		return 0;
	case SMI_EVENT_GBL_RLS:
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
				ICH2_SMI_EN_BIOS_EN);
		return 0;
	case SMI_EVENT_PWRBTN:
		outl(_get_PMBASE() + ICH2_PMBASE_PM1_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_PM1_EN) |
				ICH2_PM1_EN_PWRBTN_EN);
		return 0;
	default:
		return -1;
	}
}

int smi_disable_event(smi_event_t ev)
{
	switch(ev)
	{
	case SMI_EVENT_FAST_TIMER:
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
				~ICH2_SMI_EN_SWSMI_TMR_EN);
		return 0;
	case SMI_EVENT_DEVTRAP_KBC:
		outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
				~ICH2_DEVTRAP_EN_KBC_TRP_EN);
		return 0;
	case SMI_EVENT_GBL_RLS:
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
				~ICH2_SMI_EN_BIOS_EN);
		return 0;
	case SMI_EVENT_PWRBTN:
		outl(_get_PMBASE() + ICH2_PMBASE_PM1_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_PM1_EN) &
				~ICH2_PM1_EN_PWRBTN_EN);
		return 0;
	default:
		return -1;
	}
}
Commit	Line	Data
f1584bb0 JW	1	/* smi.c
	2	* System management interrupt dispatch routines for ICH2 southbridge
	3	* NetWatch system management mode administration console
	4	*
	5	* Copyright (c) 2008 Jacob Potter and Joshua Wise. All rights reserved.
	6	* This program is free software; you can redistribute and/or modify it under
	7	* the terms found in the file LICENSE in the root of this source tree.
	8	*
	9	*/
	10
	11
85bc8ca6 JW	12	#include <smi.h>
	13	#include <pci.h>
	14	#include <io.h>
	15	#include <stdint.h>
4fb81ad0	16	#include <vga-overlay.h>
cc80dccf	17	#include <reg-82801b.h>
efea5b4e	18	#include <output.h>
85bc8ca6	19
07d1dd26 JW	20	static smi_handler_t _handlers[SMI_EVENT_MAX] = {0};
07d1dd26 JW	21
9cfcd0ca	22	static uint16_t _get_PMBASE()
85bc8ca6	23	{
199c2b1b JW	24	static long pmbase = -1;
	25
	26	if (pmbase == -1) /* Memoize it so that we don't have to hit PCI so often. */
	27	pmbase = pci_read32(ICH2_LPC_BUS, ICH2_LPC_DEV, ICH2_LPC_FN, ICH2_LPC_PCI_PMBASE) & ICH2_PMBASE_MASK;
	28
	29	return pmbase;
85bc8ca6 JW	30	}
	31
	32	void smi_disable()
	33	{
cc80dccf JW	34	unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
cc80dccf JW	35	outl(smi_en, inl(smi_en) & ~ICH2_SMI_EN_GBL_SMI_EN);
2768393f JW	36
	37	/* Try really hard to shut up USB_LEGKEY. */
	38	pci_write16(ICH2_USB0_BUS, ICH2_USB0_DEV, ICH2_USB0_FN, ICH2_USB_LEGKEY, 0x0);
	39	pci_write16(ICH2_USB0_BUS, ICH2_USB0_DEV, ICH2_USB0_FN, ICH2_USB_LEGKEY,
	40	pci_read16(ICH2_USB0_BUS, ICH2_USB0_DEV, ICH2_USB0_FN, ICH2_USB_LEGKEY));
	41	pci_write16(ICH2_USB1_BUS, ICH2_USB1_DEV, ICH2_USB1_FN, ICH2_USB_LEGKEY, 0x0);
	42	pci_write16(ICH2_USB1_BUS, ICH2_USB1_DEV, ICH2_USB1_FN, ICH2_USB_LEGKEY,
	43	pci_read16(ICH2_USB1_BUS, ICH2_USB1_DEV, ICH2_USB1_FN, ICH2_USB_LEGKEY));
	44
85bc8ca6 JW	45	}
	46
	47	void smi_enable()
	48	{
cc80dccf JW	49	unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
cc80dccf JW	50	outl(smi_en, inl(smi_en) \| ICH2_SMI_EN_GBL_SMI_EN);
85bc8ca6 JW	51	}
	52
	53	unsigned long smi_status()
	54	{
cc80dccf	55	unsigned short smi_sts = _get_PMBASE() + ICH2_PMBASE_SMI_STS;
85bc8ca6 JW	56	return inl(smi_sts);
85bc8ca6 JW	57	}
d71d9872	58
4fb81ad0 JW	59	void smi_poll()
	60	{
	61	unsigned long sts = smi_status();
	62
	63	if (sts & ICH2_SMI_STS_BIOS_STS)
	64	{
73fb9b4c JW	65	if (_handlers[SMI_EVENT_GBL_RLS] == SMI_HANDLER_NONE)
	66	output("Unhandled: BIOS_STS");
	67	else if (_handlers[SMI_EVENT_GBL_RLS] != SMI_HANDLER_IGNORE)
	68	_handlers[SMI_EVENT_GBL_RLS](SMI_EVENT_GBL_RLS);
4fb81ad0 JW	69	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
	70	}
	71
	72	if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
	73	{
efea5b4e	74	output("Unhandled: LEGACY_USB_STS");
4fb81ad0 JW	75	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
	76	}
	77
	78	if (sts & ICH2_SMI_STS_SLP_SMI_STS)
	79	{
efea5b4e	80	output("Unhandled: SLP_SMI_STS");
4fb81ad0 JW	81	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
	82	}
	83
	84	if (sts & ICH2_SMI_STS_APM_STS)
	85	{
efea5b4e	86	output("Unhandled: APM_STS");
199c2b1b	87	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_APM_STS);
4fb81ad0 JW	88	}
	89
	90	if (sts & ICH2_SMI_STS_SWSMI_TMR_STS) // Ack it, then request another.
	91	{
07d1dd26 JW	92	if (_handlers[SMI_EVENT_FAST_TIMER] == SMI_HANDLER_NONE)
	93	output("Unhandled: SWSMI_TMR_STS");
	94	else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
	95	_handlers[SMI_EVENT_FAST_TIMER](SMI_EVENT_FAST_TIMER);
199c2b1b	96	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SWSMI_TMR_STS);
4fb81ad0 JW	97	}
	98
	99	if (sts & ICH2_SMI_STS_PM1_STS_REG)
	100	{
199c2b1b JW	101	unsigned short pm1_sts = inw(_get_PMBASE() + ICH2_PMBASE_PM1_STS);
	102	unsigned short pm1_en = inw(_get_PMBASE() + ICH2_PMBASE_PM1_EN);
	103
	104	pm1_sts &= pm1_en;
	105	if (pm1_sts & ICH2_PM1_STS_RTC_STS)
	106	{
efea5b4e	107	output("Unhandled: PM1_STS: RTC_STS");
199c2b1b JW	108	outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
	109	}
	110
	111	if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
	112	{
47d8a487 JW	113	if (_handlers[SMI_EVENT_PWRBTN] == SMI_HANDLER_NONE)
	114	output("Unhandled: PM1_STS: PWRBTN_STS");
	115	else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
	116	_handlers[SMI_EVENT_PWRBTN](SMI_EVENT_PWRBTN);
199c2b1b JW	117	outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
	118	}
	119
	120	if (pm1_sts & ICH2_PM1_STS_GBL_STS)
	121	{
efea5b4e	122	output("Unhandled: PM1_STS: GBL_STS");
199c2b1b JW	123	outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
	124	}
	125
	126	if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
	127	{
efea5b4e	128	output("Unhandled: PM1_STS: TMROF_STS");
199c2b1b JW	129	outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_TMROF_STS);
	130	}
	131
	132	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PM1_STS_REG);
4fb81ad0 JW	133	}
	134
	135	if (sts & ICH2_SMI_STS_GPE0_STS)
	136	{
	137	/* XXX -- trawl through GPE0_STS to see what happened */
efea5b4e	138	output("XXX Unhandled: GPE0_STS (expect lockup)");
199c2b1b JW	139	}
	140
	141	if (sts & ICH2_SMI_STS_GPE1_STS)
	142	{
	143	/* XXX -- trawl through GPE1_STS to see what happened */
efea5b4e	144	output("XXX Unhandled: GPE1_STS (expect lockup)");
4fb81ad0 JW	145	}
	146
	147	if (sts & ICH2_SMI_STS_MCSMI_STS)
	148	{
efea5b4e	149	output("Unhandled: MCSMI_STS");
4fb81ad0 JW	150	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_MCSMI_STS);
	151	}
	152
	153	if (sts & ICH2_SMI_STS_DEVMON_STS)
	154	{
199c2b1b JW	155	unsigned short mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
	156	unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
	157	unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
8a677ebb JW	158
	159	if (devact_sts & ICH2_DEVACT_STS_KBC_ACT_STS)
	160	{
	161	if (_handlers[SMI_EVENT_DEVTRAP_KBC] == SMI_HANDLER_NONE)
	162	output("Unhandled: DEVACT_KBC_ACT_STS");
	163	else if (_handlers[SMI_EVENT_DEVTRAP_KBC] != SMI_HANDLER_IGNORE)
	164	_handlers[SMI_EVENT_DEVTRAP_KBC](SMI_EVENT_DEVTRAP_KBC);
	165	outl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS, ICH2_DEVACT_STS_KBC_ACT_STS);
	166	}
	167
	168	/* Refresh register cache so that we can print unhandleds as needed. */
	169	mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
	170	devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
	171	devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
	172
199c2b1b	173	if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
efea5b4e	174	outputf("Unhandled: MON_SMI (%04x)", mon_smi);
199c2b1b	175	if (devact_sts & devtrap_en)
efea5b4e	176	outputf("Unhandled: DEVTRAP (%08x)", devact_sts & devtrap_en);
4fb81ad0 JW	177	}
	178
	179	if (sts & ICH2_SMI_STS_TCO_STS)
	180	{
efea5b4e	181	output("Unhandled: TCO_STS");
4fb81ad0 JW	182	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
	183	}
	184
	185	if (sts & ICH2_SMI_STS_PERIODIC_STS)
	186	{
efea5b4e	187	output("Unhandled: PERIODIC_STS");
4fb81ad0 JW	188	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
	189	}
	190
	191	if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
	192	{
efea5b4e	193	output("Unhandled: SERIRQ_SMI_STS");
4fb81ad0 JW	194	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
	195	}
	196
	197	if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
	198	{
efea5b4e	199	output("Unhandled: SMBUS_SMI_STS");
4fb81ad0 JW	200	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
	201	}
	202
199c2b1b	203	if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG) /* Either the chipset is buggy, or we are. */
efea5b4e	204	outputf("WARN: couldn't clear SMI_STS! (%08x)", smi_status());
4fb81ad0 JW	205
	206	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	207	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) \|
	208	ICH2_SMI_EN_EOS \|
	209	ICH2_SMI_EN_GBL_SMI_EN);
	210	}
07d1dd26 JW	211
	212	int smi_register_handler(smi_event_t ev, smi_handler_t hnd)
	213	{
	214	if (ev >= SMI_EVENT_MAX)
	215	return -1;
	216	_handlers[ev] = hnd;
	217	return 0;
	218	}
	219
	220	int smi_enable_event(smi_event_t ev)
	221	{
	222	switch(ev)
	223	{
	224	case SMI_EVENT_FAST_TIMER:
	225	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	226	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) \|
	227	ICH2_SMI_EN_SWSMI_TMR_EN);
	228	return 0;
8a677ebb JW	229	case SMI_EVENT_DEVTRAP_KBC:
	230	outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
	231	inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) \|
	232	ICH2_DEVTRAP_EN_KBC_TRP_EN);
	233	return 0;
73fb9b4c JW	234	case SMI_EVENT_GBL_RLS:
	235	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	236	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) \|
	237	ICH2_SMI_EN_BIOS_EN);
	238	return 0;
47d8a487 JW	239	case SMI_EVENT_PWRBTN:
	240	outl(_get_PMBASE() + ICH2_PMBASE_PM1_EN,
	241	inl(_get_PMBASE() + ICH2_PMBASE_PM1_EN) \|
	242	ICH2_PM1_EN_PWRBTN_EN);
	243	return 0;
07d1dd26 JW	244	default:
	245	return -1;
	246	}
	247	}
	248
	249	int smi_disable_event(smi_event_t ev)
	250	{
	251	switch(ev)
	252	{
	253	case SMI_EVENT_FAST_TIMER:
	254	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	255	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
	256	~ICH2_SMI_EN_SWSMI_TMR_EN);
	257	return 0;
8a677ebb JW	258	case SMI_EVENT_DEVTRAP_KBC:
	259	outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
	260	inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
	261	~ICH2_DEVTRAP_EN_KBC_TRP_EN);
	262	return 0;
73fb9b4c JW	263	case SMI_EVENT_GBL_RLS:
	264	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	265	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
	266	~ICH2_SMI_EN_BIOS_EN);
	267	return 0;
47d8a487 JW	268	case SMI_EVENT_PWRBTN:
	269	outl(_get_PMBASE() + ICH2_PMBASE_PM1_EN,
	270	inl(_get_PMBASE() + ICH2_PMBASE_PM1_EN) &
	271	~ICH2_PM1_EN_PWRBTN_EN);
	272	return 0;
07d1dd26 JW	273	default:
	274	return -1;
	275	}
	276	}