Merge branch 'master' of andrew:/afs/andrew/usr/czl/public/FPGABoy

diff --git a/CoreTop.ucf b/CoreTop.ucf
index 55b46529613be37c8d61fe04b0e9d4da6d3d504a..5e374104b662cbcb2bbb10d81b8d3903b06cf629 100644 (file)
--- a/CoreTop.ucf
+++ b/CoreTop.ucf
@@ -103,5 +103,8 @@ NET "cr_A<20>" LOC="K3" | SLEW="fast";
 NET "cr_A<21>" LOC="D1" | SLEW="fast";
 NET "cr_A<22>" LOC="K6" | SLEW="fast";
 
+NET "st_nCE" LOC="R5" | SLEW="fast";
+NET "st_nRST" LOC="T5" | SLEW="fast";
+
 NET "ps2c" LOC="R12" | CLOCK_DEDICATED_ROUTE = FALSE;
-NET "ps2d" LOC="P11";
\ No newline at end of file
+NET "ps2d" LOC="P11";

diff --git a/LCDC.v b/LCDC.v
index cb204d5df1e5c6b58b0761cd4474c099f6abf946..c550288a04df9375c35a3b9d1e03e084238e15f1 100644 (file)
--- a/LCDC.v
+++ b/LCDC.v
@@ -135,8 +135,8 @@ module LCDC(
         * Tile data from 8000-8FFF or 8800-97FF
         * Background tile maps 9800-9BFF or 9C00-9FFF
         */
-       reg [7:0] tiledatahigh [3071:0];
-       reg [7:0] tiledatalow [3071:0];
+       reg [7:0] tiledatahigh [6143:0];
+       reg [7:0] tiledatalow [6143:0];
        reg [7:0] bgmap1 [1023:0];
        reg [7:0] bgmap2 [1023:0];
        
@@ -146,14 +146,19 @@ module LCDC(
        // The new tile data is latched and ready when vxpos[2:0] is 3'b000!
        wire [7:0] vxpos_ = vxpos + 1;
        wire [9:0] bgmapaddr = {vypos[7:3], vxpos_[7:3]};
-       reg [7:0] tileno;
-       wire [10:0] tileaddr = {tileno, vypos[2:0]};
+       reg [7:0] tileno1;
+       reg [7:0] tileno2;
+       wire [7:0] tileno = rLCDC[3] ? tileno2 : tileno1;
+       wire [11:0] tileaddr =
+               {(rLCDC[4] ? {1'b0,tileno} : (9'b100000000 + {tileno[7],tileno})),
+               vypos[2:0]};
        reg [7:0] tilehigh, tilelow;
        wire [1:0] prepal = {tilehigh[7-vxpos[2:0]], tilelow[7-vxpos[2:0]]};
        assign pixdata = 2'b11-{rBGP[{prepal,1'b1}],rBGP[{prepal,1'b0}]};
        
        wire decode_tiledata = (addr >= 16'h8000) && (addr <= 16'h97FF);
        wire decode_bgmap1 = (addr >= 16'h9800) && (addr <= 16'h9BFF);
+       wire decode_bgmap2 = (addr >= 16'h9C00) && (addr <= 16'h9FFF);
 
        wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0];
        wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];
@@ -161,10 +166,15 @@ module LCDC(
        always @(posedge clk)
        begin
                if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap1) begin
-                       tileno <= bgmap1[bgmapaddr_in];
+                       tileno1 <= bgmap1[bgmapaddr_in];
                        if (wr && decode_bgmap1 && ~vraminuse)
                                bgmap1[bgmapaddr_in] <= data;
                end
+               if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap2) begin
+                       tileno2 <= bgmap2[bgmapaddr_in];
+                       if (wr && decode_bgmap2 && ~vraminuse)
+                               bgmap2[bgmapaddr_in] <= data;
+               end
                if ((vraminuse && ((posx == 3) || (vxpos[2:0] == 3'b000))) || decode_tiledata) begin
                        tilehigh <= tiledatahigh[tileaddr_in];
                        tilelow <= tiledatalow[tileaddr_in];

diff --git a/System.v b/System.v
index 02b424cf54b03a366359019648aff429c90243e7..e0baebe3c65f9dad345554cc8137b35010ed4282 100644 (file)
--- a/System.v
+++ b/System.v
@@ -81,6 +81,7 @@ module CellularRAM(
        inout [7:0] data,
        input wr, rd,
        output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+       output wire st_nCE, st_nRST,
        output wire [22:0] cr_A,
        inout [15:0] cr_DQ);
        
@@ -88,6 +89,7 @@ module CellularRAM(
        parameter ADDR_PROGADDRM = 16'hFF61;
        parameter ADDR_PROGADDRL = 16'hFF62;
        parameter ADDR_PROGDATA = 16'hFF63;
+       parameter ADDR_PROGFLASH = 16'hFF65;
        parameter ADDR_MBC = 16'hFF64;
        
        reg rdlatch = 0, wrlatch = 0;
@@ -102,25 +104,28 @@ module CellularRAM(
                                                // low 7 bits are the MBC that we are emulating
        
        assign cr_nADV = 0;     /* Addresses are always valid! :D */
-       assign cr_nCE = 0;      /* The chip is enabled */
+       assign cr_nCE = ~(addrlatch != ADDR_PROGFLASH); /* The chip is enabled */
        assign cr_nLB = 0;      /* Lower byte is enabled */
        assign cr_nUB = 0;      /* Upper byte is enabled */
        assign cr_CRE = 0;      /* Data writes, not config */
        assign cr_CLK = 0;      /* Clock? I think not! */
        
-       wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA);
+       assign st_nRST = 1;     /* Keep the strataflash out of reset. */
+       assign st_nCE = ~(addrlatch == ADDR_PROGFLASH);
+       
+       wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH);
        
        reg [3:0] rambank = 0;
        reg [8:0] rombank = 1;
        
        assign cr_nOE = decode ? ~rdlatch : 1;
-       assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;
+       assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;
        
        assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
        assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
                        (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
                        (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
-                       (addrlatch == ADDR_PROGDATA) ? progaddr :
+                       ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH)) ? progaddr :
                        23'b0;
        
        always @(posedge clk) begin
@@ -229,7 +234,7 @@ module CoreTop(
        input serin,
        output wire [3:0] digits,
        output wire [7:0] seven,
-       output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
+       output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, st_nCE, st_nRST,
        output wire [22:0] cr_A,
        inout [15:0] cr_DQ,
        input ps2c, ps2d,
@@ -314,7 +319,9 @@ module CoreTop(
                .cr_nUB(cr_nUB),
                .cr_CLK(cr_CLK),
                .cr_A(cr_A),
-               .cr_DQ(cr_DQ));
+               .cr_DQ(cr_DQ),
+               .st_nCE(st_nCE),
+               .st_nRST(st_nRST));
 `endif
        
        wire lcdhs, lcdvs, lcdclk;

diff --git a/core/insn_add_hl.v b/core/insn_add_hl.v
index 0d85f953f5713ec704c696b927a4018094d96a55..6bd7e7a8dc17e8599cf6497eeb46b835cca827fd 100644 (file)
--- a/core/insn_add_hl.v
+++ b/core/insn_add_hl.v
@@ -20,15 +20,14 @@
 `ifdef WRITEBACK
        `INSN_ADD_HL: begin
                case (cycle)
-               0:      {tmp,tmp2} <= `_HL + {tmp,tmp2};
                1:      begin
                                `_F <=  { /* Z */ `_F[7],
                                          /* N */ 1'b0,
                                          /* H */ (({`_HL} + {tmp,tmp2}) & 16'h1000) ? 1'b1 : 1'b0,
-                                         /* C */ (({1'b0,`_HL} + {1'b0,tmp,tmp2}) >> 16 == 1) ? 1'b1 : 1'b0,
+                                         /* C */ (({1'b0,`_HL} + {1'b0,tmp,tmp2}) & 17'h10000) ? 1'b1 : 1'b0,
                                          `_F[3:0]
                                        };
-                               `_HL <= {tmp, tmp2};
+                               `_HL <= `_HL + {tmp, tmp2};
                        end
                endcase
        end

diff --git a/core/insn_alu8.v b/core/insn_alu8.v
index 1283a9cfbc5c00645c79c1bf65fa78dd3271216e..26fc77eca45614d1c26c0920570413a83f959b93 100644 (file)
--- a/core/insn_alu8.v
+++ b/core/insn_alu8.v
@@ -69,21 +69,21 @@
                        end
                        `INSN_alu_AND: begin
                                `_A <= `_A & tmp;
-                               `_F <=  { /* Z */ ((`_A & tmp) == 0) ? 1'b1 : 1'b0,
+                               `_F <=  { /* Z */ ((`_A & tmp) == 8'b0) ? 1'b1 : 1'b0,
                                          3'b010,
                                          `_F[3:0]
                                        };
                        end
                        `INSN_alu_OR: begin
                                `_A <= `_A | tmp;
-                               `_F <=  { /* Z */ ((`_A | tmp) == 0) ? 1'b1 : 1'b0,
+                               `_F <=  { /* Z */ ((`_A | tmp) == 8'b0) ? 1'b1 : 1'b0,
                                          3'b000,
                                          `_F[3:0]
                                        };
                        end
                        `INSN_alu_XOR: begin
                                `_A <= `_A ^ tmp;
-                               `_F <=  { /* Z */ ((`_A ^ tmp) == 0) ? 1'b1 : 1'b0,
+                               `_F <=  { /* Z */ ((`_A ^ tmp) == 8'b0) ? 1'b1 : 1'b0,
                                          3'b000,
                                          `_F[3:0]
                                        };