System.v

   1
   2 `timescale 1ns / 1ps
   3 module SimROM(
   4         input [15:0] address,
   5         inout [7:0] data,
   6         input clk,
   7         input wr, rd);
   8
   9         reg rdlatch = 0;
  10         reg [7:0] odata;
  11
  12         reg [7:0] rom [32767:0];
  13         initial $readmemh("rom.hex", rom);
  14
  15         wire decode = address[15:13] == 0;
  16         always @(posedge clk) begin
  17                 rdlatch <= rd && decode;
  18                 odata <= rom[address[10:0]];
  19         end
  20         assign data = rdlatch ? odata : 8'bzzzzzzzz;
  21 endmodule
  22
  23 module BootstrapROM(
  24         input [15:0] address,
  25         inout [7:0] data,
  26         input clk,
  27         input wr, rd);
  28
  29         reg rdlatch = 0;
  30         reg [7:0] addrlatch = 0;
  31         reg romno = 0, romnotmp = 0;
  32         reg [7:0] brom0 [255:0];
  33         reg [7:0] brom1 [255:0];
  34
  35         initial $readmemh("fpgaboot.hex", brom0);
  36         initial $readmemh("gbboot.hex", brom1);
  37
  38 `ifdef isim
  39         initial romno <= 1;
  40 `endif
  41
  42         wire decode = address[15:8] == 0;
  43         wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
  44         always @(posedge clk) begin
  45                 rdlatch <= rd && decode;
  46                 addrlatch <= address[7:0];
  47                 if (wr && decode) romnotmp <= data[0];
  48                 if (rd && address == 16'h0000) romno <= romnotmp;       /* Latch when the program restarts. */
  49         end
  50         assign data = rdlatch ? odata : 8'bzzzzzzzz;
  51 endmodule
  52
  53 module MiniRAM(
  54         input [15:0] address,
  55         inout [7:0] data,
  56         input clk,
  57         input wr, rd);
  58
  59         reg [7:0] ram [127:0];
  60
  61         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
  62         reg rdlatch = 0;
  63         reg [7:0] odata;
  64         assign data = rdlatch ? odata : 8'bzzzzzzzz;
  65
  66         always @(posedge clk)
  67         begin
  68                 rdlatch <= rd && decode;
  69                 if (decode)             // This has to go this way. The only way XST knows how to do
  70                 begin                   // block ram is chip select, write enable, and always
  71                         if (wr)         // reading. "else if rd" does not cut it ...
  72                                 ram[address[6:0]] <= data;
  73                         odata <= ram[address[6:0]];
  74                 end
  75         end
  76 endmodule
  77
  78 module CellularRAM(
  79         input clk,
  80         input [15:0] address,
  81         inout [7:0] data,
  82         input wr, rd,
  83         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
  84         output wire st_nCE, st_nRST,
  85         output wire [22:0] cr_A,
  86         inout [15:0] cr_DQ);
  87
  88         parameter ADDR_PROGADDRH = 16'hFF60;
  89         parameter ADDR_PROGADDRM = 16'hFF61;
  90         parameter ADDR_PROGADDRL = 16'hFF62;
  91         parameter ADDR_PROGDATA = 16'hFF63;
  92         parameter ADDR_PROGFLASH = 16'hFF65;
  93         parameter ADDR_MBC = 16'hFF64;
  94
  95         reg rdlatch = 0, wrlatch = 0;
  96         reg [15:0] addrlatch = 0;
  97         reg [7:0] datalatch = 0;
  98
  99         reg [7:0] progaddrh, progaddrm, progaddrl;
 100
 101         reg [22:0] progaddr;
 102
 103         reg [7:0] mbc_emul = 8'b00000101;       // High bit is whether we're poking flash
 104                                                 // low 7 bits are the MBC that we are emulating
 105
 106         assign cr_nADV = 0;     /* Addresses are always valid! :D */
 107         assign cr_nCE = ~(addrlatch != ADDR_PROGFLASH); /* The chip is enabled */
 108         assign cr_nLB = 0;      /* Lower byte is enabled */
 109         assign cr_nUB = 0;      /* Upper byte is enabled */
 110         assign cr_CRE = 0;      /* Data writes, not config */
 111         assign cr_CLK = 0;      /* Clock? I think not! */
 112
 113         assign st_nRST = 1;     /* Keep the strataflash out of reset. */
 114         assign st_nCE = ~(addrlatch == ADDR_PROGFLASH);
 115
 116         wire decode = (addrlatch[15:14] == 2'b00) /* extrom */ || (addrlatch[15:13] == 3'b101) /* extram */ || (addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH);
 117
 118         reg [3:0] rambank = 0;
 119         reg [8:0] rombank = 1;
 120
 121         assign cr_nOE = decode ? ~rdlatch : 1;
 122         assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;
 123
 124         assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
 125         assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :
 126                         (addrlatch[15:14] == 2'b01) ? /* extrom, paged bank */ {rombank, addrlatch[13:0]} :
 127                         (addrlatch[15:13] == 3'b101) ? /* extram */ {1'b1, 5'b0, rambank, addrlatch[12:0]} :
 128                         ((addrlatch == ADDR_PROGDATA) || (addrlatch == ADDR_PROGFLASH)) ? progaddr :
 129                         23'b0;
 130
 131         always @(posedge clk) begin
 132                 case (address)
 133                 ADDR_PROGADDRH: if (wr) progaddrh <= data;
 134                 ADDR_PROGADDRM: if (wr) progaddrm <= data;
 135                 ADDR_PROGADDRL: if (wr) progaddrl <= data;
 136                 ADDR_PROGDATA:  if (rd || wr) begin
 137                                         progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
 138                                         {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
 139                                 end
 140                 ADDR_MBC:       begin
 141                                         mbc_emul <= data;
 142                                         rambank <= 0;
 143                                         rombank <= 1;
 144                                 end
 145                 endcase
 146
 147                 if (mbc_emul[6:0] == 5) begin
 148                         if ((address[15:12] == 4'h2) && wr)
 149                                 rombank <= {rombank[8], data};
 150                         else if ((address[15:12] == 4'h3) && wr)
 151                                 rombank <= {data[0], rombank[7:0]};
 152                         else if ((address[15:12] == 4'h4) && wr)
 153                                 rambank <= data[3:0];
 154                 end
 155
 156                 rdlatch <= rd;
 157                 wrlatch <= wr;
 158                 addrlatch <= address;
 159                 datalatch <= data;
 160         end
 161
 162         assign data = (rdlatch && decode) ?
 163                                 (addrlatch == ADDR_PROGADDRH) ? progaddrh :
 164                                 (addrlatch == ADDR_PROGADDRM) ? progaddrm :
 165                                 (addrlatch == ADDR_PROGADDRL) ? progaddrl :
 166                                 cr_DQ
 167                         : 8'bzzzzzzzz;
 168 endmodule
 169
 170 module InternalRAM(
 171         input [15:0] address,
 172         inout [7:0] data,
 173         input clk,
 174         input wr, rd);
 175
 176         // synthesis attribute ram_style of ram is block
 177         reg [7:0] ram [8191:0];
 178
 179         wire decode = (address >= 16'hC000) && (address <= 16'hFDFF);   /* This includes echo RAM. */
 180         reg [7:0] odata;
 181         reg rdlatch = 0;
 182         assign data = rdlatch ? odata : 8'bzzzzzzzz;
 183
 184         always @(posedge clk)
 185         begin
 186                 rdlatch <= rd && decode;
 187                 if (decode)             // This has to go this way. The only way XST knows how to do
 188                 begin                   // block ram is chip select, write enable, and always
 189                         if (wr)         // reading. "else if rd" does not cut it ...
 190                                 ram[address[12:0]] <= data;
 191                         odata <= ram[address[12:0]];
 192                 end
 193         end
 194 endmodule
 195
 196 module Switches(
 197         input [15:0] address,
 198         inout [7:0] data,
 199         input clk,
 200         input wr, rd,
 201         input [7:0] switches,
 202         output reg [7:0] ledout = 0);
 203
 204         wire decode = address == 16'hFF51;
 205         reg [7:0] odata;
 206         reg rdlatch = 0;
 207         assign data = rdlatch ? odata : 8'bzzzzzzzz;
 208
 209         always @(posedge clk)
 210         begin
 211                 rdlatch <= rd && decode;
 212                 if (decode && rd)
 213                         odata <= switches;
 214                 else if (decode && wr)
 215                         ledout <= data;
 216         end
 217 endmodule
 218
 219 `ifdef isim
 220 module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
 221 endmodule
 222 `endif
 223
 224 module CoreTop(
 225 `ifdef isim
 226         output reg vgaclk = 0,
 227         output reg clk = 0,
 228 `else
 229         input xtal,
 230         input [7:0] switches,
 231         input [3:0] buttons,
 232         output wire [7:0] leds,
 233         output serio,
 234         input serin,
 235         output wire [3:0] digits,
 236         output wire [7:0] seven,
 237         output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK, st_nCE, st_nRST,
 238         output wire [22:0] cr_A,
 239         inout [15:0] cr_DQ,
 240         input ps2c, ps2d,
 241 `endif
 242         output wire hs, vs,
 243         output wire [2:0] r, g,
 244         output wire [1:0] b,
 245         output wire soundl, soundr);
 246
 247 `ifdef isim
 248         always #62 clk <= ~clk;
 249         always #100 vgaclk <= ~vgaclk;
 250
 251         Dumpable dump(r,g,b,hs,vs,vgaclk);
 252
 253         wire [7:0] leds;
 254         wire serio;
 255         wire serin = 1;
 256         wire [3:0] digits;
 257         wire [7:0] seven;
 258         wire [7:0] switches = 8'b0;
 259         wire [3:0] buttons = 4'b0;
 260 `else
 261         wire xtalb, clk, vgaclk;
 262         IBUFG iclkbuf(.O(xtalb), .I(xtal));
 263         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
 264         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
 265         wire [7:0] ps2buttons;
 266 `endif
 267
 268         wire [15:0] addr [1:0];
 269         wire [7:0] data [1:0];
 270         wire wr [1:0], rd [1:0];
 271
 272         wire irq, tmrirq, lcdcirq, vblankirq, btnirq;
 273         wire [7:0] jaddr;
 274         wire [1:0] state;
 275         wire ack;
 276
 277         GBZ80Core core(
 278                 .clk(clk),
 279                 .bus0address(addr[0]),
 280                 .bus0data(data[0]),
 281                 .bus0wr(wr[0]),
 282                 .bus0rd(rd[0]),
 283                 .bus1address(addr[1]),
 284                 .bus1data(data[1]),
 285                 .bus1wr(wr[1]),
 286                 .bus1rd(rd[1]),
 287                 .irq(irq),
 288                 .irqack(ack),
 289                 .jaddr(jaddr),
 290                 .state(state));
 291
 292         BootstrapROM brom(
 293                 .address(addr[1]),
 294                 .data(data[1]),
 295                 .clk(clk),
 296                 .wr(wr[1]),
 297                 .rd(rd[1]));
 298
 299 `ifdef isim
 300         SimROM rom(
 301                 .address(addr[0]),
 302                 .data(data[0]),
 303                 .clk(clk),
 304                 .wr(wr[0]),
 305                 .rd(rd[0]));
 306 `else
 307         CellularRAM cellram(
 308                 .address(addr[0]),
 309                 .data(data[0]),
 310                 .clk(clk),
 311                 .wr(wr[0]),
 312                 .rd(rd[0]),
 313                 .cr_nADV(cr_nADV),
 314                 .cr_nCE(cr_nCE),
 315                 .cr_nOE(cr_nOE),
 316                 .cr_nWE(cr_nWE),
 317                 .cr_CRE(cr_CRE),
 318                 .cr_nLB(cr_nLB),
 319                 .cr_nUB(cr_nUB),
 320                 .cr_CLK(cr_CLK),
 321                 .cr_A(cr_A),
 322                 .cr_DQ(cr_DQ),
 323                 .st_nCE(st_nCE),
 324                 .st_nRST(st_nRST));
 325 `endif
 326
 327         wire lcdhs, lcdvs, lcdclk;
 328         wire [2:0] lcdr, lcdg;
 329         wire [1:0] lcdb;
 330
 331         LCDC lcdc(
 332                 .clk(clk),
 333                 .addr(addr[0]),
 334                 .data(data[0]),
 335                 .wr(wr[0]),
 336                 .rd(rd[0]),
 337                 .lcdcirq(lcdcirq),
 338                 .vblankirq(vblankirq),
 339                 .lcdclk(lcdclk),
 340                 .lcdhs(lcdhs),
 341                 .lcdvs(lcdvs),
 342                 .lcdr(lcdr),
 343                 .lcdg(lcdg),
 344                 .lcdb(lcdb));
 345
 346         Framebuffer fb(
 347                 .lcdclk(lcdclk),
 348                 .lcdhs(lcdhs),
 349                 .lcdvs(lcdvs),
 350                 .lcdr(lcdr),
 351                 .lcdg(lcdg),
 352                 .lcdb(lcdb),
 353                 .vgaclk(vgaclk),
 354                 .vgahs(hs),
 355                 .vgavs(vs),
 356                 .vgar(r),
 357                 .vgag(g),
 358                 .vgab(b));
 359
 360         wire [7:0] sleds;
 361 `ifdef isim
 362         assign leds = sleds;
 363 `else
 364         assign leds = sleds | ps2buttons;
 365 `endif
 366         Switches sw(
 367                 .clk(clk),
 368                 .address(addr[0]),
 369                 .data(data[0]),
 370                 .wr(wr[0]),
 371                 .rd(rd[0]),
 372                 .ledout(sleds),
 373                 .switches(switches)
 374                 );
 375
 376 `ifdef isim
 377 `else
 378         PS2Button ps2(
 379                 .clk(clk),
 380                 .inclk(ps2c),
 381                 .indata(ps2d),
 382                 .buttons(ps2buttons)
 383                 );
 384 `endif
 385
 386         Buttons ass(
 387                 .core_clk(clk),
 388                 .addr(addr[0]),
 389                 .data(data[0]),
 390                 .wr(wr[0]),
 391                 .rd(rd[0]),
 392                 .int(btnirq),
 393         `ifdef isim
 394                 .buttons(switches)
 395         `else
 396                 .buttons(ps2buttons)
 397         `endif
 398                 );
 399
 400         AddrMon amon(
 401                 .clk(clk),
 402                 .addr(addr[0]),
 403                 .digit(digits),
 404                 .out(seven),
 405                 .freeze(buttons[0]),
 406                 .periods(
 407                         (state == 2'b00) ? 4'b0010 :
 408                         (state == 2'b01) ? 4'b0001 :
 409                         (state == 2'b10) ? 4'b1000 :
 410                                            4'b0100) );
 411
 412         UART nouart (   /* no u */
 413                 .clk(clk),
 414                 .addr(addr[0]),
 415                 .data(data[0]),
 416                 .wr(wr[0]),
 417                 .rd(rd[0]),
 418                 .serial(serio),
 419                 .serialrx(serin)
 420                 );
 421
 422         InternalRAM ram(
 423                 .clk(clk),
 424                 .address(addr[0]),
 425                 .data(data[0]),
 426                 .wr(wr[0]),
 427                 .rd(rd[0])
 428                 );
 429
 430         MiniRAM mram(
 431                 .clk(clk),
 432                 .address(addr[1]),
 433                 .data(data[1]),
 434                 .wr(wr[1]),
 435                 .rd(rd[1])
 436                 );
 437
 438         Timer tmr(
 439                 .clk(clk),
 440                 .addr(addr[0]),
 441                 .data(data[0]),
 442                 .wr(wr[0]),
 443                 .rd(rd[0]),
 444                 .irq(tmrirq)
 445                 );
 446
 447         Interrupt intr(
 448                 .clk(clk),
 449                 .addr(addr[0]),
 450                 .data(data[0]),
 451                 .wr(wr[0]),
 452                 .rd(rd[0]),
 453                 .vblank(vblankirq),
 454                 .lcdc(lcdcirq),
 455                 .tovf(tmrirq),
 456                 .serial(1'b0),
 457                 .buttons(btnirq),
 458                 .master(irq),
 459                 .ack(ack),
 460                 .jaddr(jaddr));
 461
 462         Soundcore sound(
 463                 .core_clk(clk),
 464                 .addr(addr[0]),
 465                 .data(data[0]),
 466                 .rd(rd[0]),
 467                 .wr(wr[0]),
 468                 .snd_data_l(soundl),
 469                 .snd_data_r(soundr));
 470 endmodule