Merge branch 'master' of andrew:/afs/andrew/usr/czl/public/FPGABoy
[fpgaboy.git] / core / insn_add_hl.v
1 `define INSN_ADD_HL             9'b000xx1001
2
3 `ifdef EXECUTE
4         `INSN_ADD_HL: begin
5                 case (cycle)
6                 0:      case (opcode[5:4])
7                         `INSN_reg16_BC: {tmp,tmp2} <= `_BC;
8                         `INSN_reg16_DE: {tmp,tmp2} <= `_DE;
9                         `INSN_reg16_HL: {tmp,tmp2} <= `_HL;
10                         `INSN_reg16_SP: {tmp,tmp2} <= `_SP;
11                         endcase
12                 1:      begin
13                                 `EXEC_INC_PC
14                                 `EXEC_NEWCYCLE
15                         end
16                 endcase
17         end
18 `endif
19
20 `ifdef WRITEBACK
21         `INSN_ADD_HL: begin
22                 case (cycle)
23                 1:      begin
24                                 `_F <=  { /* Z */ `_F[7],
25                                           /* N */ 1'b0,
26                                           /* H */ (({`_HL} + {tmp,tmp2}) & 16'h1000) ? 1'b1 : 1'b0,
27                                           /* C */ (({1'b0,`_HL} + {1'b0,tmp,tmp2}) & 17'h10000) ? 1'b1 : 1'b0,
28                                           `_F[3:0]
29                                         };
30                                 `_HL <= `_HL + {tmp, tmp2};
31                         end
32                 endcase
33         end
34 `endif
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