]> Joshua Wise's Git repositories - fpgaboy.git/commitdiff
alu_ext
authorJoshua Wise <joshua@nyus.joshuawise.com>
Sat, 19 Apr 2008 10:12:53 +0000 (06:12 -0400)
committerJoshua Wise <joshua@nyus.joshuawise.com>
Sat, 19 Apr 2008 10:12:53 +0000 (06:12 -0400)
Makefile
System.v
allinsns.v
bootrom.asm
insn_alu_ext.v [new file with mode: 0644]

index 8b2feed5f306326d2f728ead88ebe0d01130c13b..fae41fe0279c1aeb6d5ef02900c859316cf8f342 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -6,7 +6,7 @@ VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \
        insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \
        insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \
        Timer.v LCDC.v insn_ldm8_a.v insn_ldm16_a.v Framebuffer.v \
-       insn_ldbcde_a.v
+       insn_ldbcde_a.v insn_alu_ext.v insn_bit.v insn_two_byte.v
 
 all: CoreTop_rom.svf CoreTop_diag.svf CoreTop_bootrom.svf CoreTop.twr
 
index 0e464f52d24eb286cae3fb680816c56988ed73f8..caa6ae34024a08e6f4444f3f5a264ba762cbfaa2 100644 (file)
--- a/System.v
+++ b/System.v
@@ -36,6 +36,7 @@ module MiniRAM(                       /* XXX will need to go INSIDE the CPU for when we do DMA */
                        odata <= ram[address[6:0]];
                end
        end
+endmodule
 
 module InternalRAM(
        input [15:0] address,
index 5ca51d691a8f42a0ca2cb40a17f2dbb12b2b8934..6c1c487260f7407c9edd560410aa9c10031cd6eb 100644 (file)
@@ -28,3 +28,4 @@
 `include "insn_ldbcde_a.v"
 `include "insn_two_byte.v"
 `include "insn_bit.v"
+`include "insn_alu_ext.v"
index 4f71d5ef23cce76e0c4de9076ed16adc1b740fee..b2a2db869afc157235ce852f77dc8f3d4796bf4b 100644 (file)
@@ -28,8 +28,8 @@ Addr_0007:
        LD HL,$8010             ; $0024
 Addr_0027:
        LD A,[DE]               ; $0027
-       CALL $0095              ; $0028
-       CALL $0096              ; $002b
+       CALL a95                ; $0028
+       CALL a96                ; $002b
        INC DE          ; $002e
        LD A,E          ; $002f
        CP $34          ; $0030
@@ -112,8 +112,8 @@ Addr_0086:
 
        ; ==== Graphic routine ====
 
-       LD C,A          ; $0095  "Double up" all the bits of the graphics data
-       LD B,$04                ; $0096     and store in Video RAM
+a95:   LD C,A          ; $0095  "Double up" all the bits of the graphics data
+a96:   LD B,$04                ; $0096     and store in Video RAM
 Addr_0098:
        PUSH BC         ; $0098
        RL C                    ; $0099
diff --git a/insn_alu_ext.v b/insn_alu_ext.v
new file mode 100644 (file)
index 0000000..1b7825b
--- /dev/null
@@ -0,0 +1,45 @@
+`ifdef EXECUTE
+       `INSN_ALU_EXT: begin
+               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
+                       `EXEC_READ(`_HL)
+               else begin
+                       `EXEC_INC_PC
+                       case (opcode[2:0])
+                       `INSN_reg_A:    tmp <= `_A;
+                       `INSN_reg_B:    tmp <= `_B;
+                       `INSN_reg_C:    tmp <= `_C;
+                       `INSN_reg_D:    tmp <= `_D;
+                       `INSN_reg_E:    tmp <= `_E;
+                       `INSN_reg_H:    tmp <= `_H;
+                       `INSN_reg_L:    tmp <= `_L;
+                       `INSN_reg_dHL:  tmp <= rdata;
+                       endcase
+               end
+       end
+`endif
+
+`ifdef WRITEBACK
+       `INSN_ALU_EXT: begin
+               if (opcode[2:0] == `INSN_reg_dHL) begin
+                       if(cycle == 0) begin end
+                       else if(cycle == 1) begin
+                               `EXEC_WRITE(`_HL, alu_res)
+                       end else begin
+                               `EXEC_NEWCYCLE
+                       end
+               end else begin
+                       case(opcode[2:0])
+                       `INSN_reg_B: `_B <= alu_res;
+                       `INSN_reg_C: `_C <= alu_res;
+                       `INSN_reg_D: `_D <= alu_res;
+                       `INSN_reg_E: `_E <= alu_res;
+                       `INSN_reg_H: `_H <= alu_res;
+                       `INSN_reg_L: `_L <= alu_res;
+                       `INSN_reg_A: `_A <= alu_res;
+                       `INSN_reg_dHL: begin end /* eat dicks */
+                       endcase
+                       `_F <= {f_res,`_F[3:0]};
+                       `EXEC_NEWCYCLE
+               end
+       end
+`endif
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