alu_ext
[fpgaboy.git] / Makefile
CommitLineData
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1VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \
2 insn_jr-jrcc.v insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v \
3 insn_ret-retcc.v Interrupt.v Uart.v allinsns.v insn_alu8.v \
4 insn_di-ei.v insn_jp_hl.v insn_ldh_ac.v insn_ld_reg_imm16.v \
5 insn_ld_sp_hl.v insn_pop_reg.v insn_rst.v System.v CPUDCM.v \
6 insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \
7 insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \
4fd47c85 8 Timer.v LCDC.v insn_ldm8_a.v insn_ldm16_a.v Framebuffer.v \
c279b666 9 insn_ldbcde_a.v insn_alu_ext.v insn_bit.v insn_two_byte.v
9c834ff2 10
6bd4619b 11all: CoreTop_rom.svf CoreTop_diag.svf CoreTop_bootrom.svf CoreTop.twr
9c834ff2 12
6c46357c 13CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS)
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14 xst -ifn CoreTop.xst -ofn CoreTop.syr
15
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16CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf
17 ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -bm "foo.bmm" -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd
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18
19CoreTop_map.ncd: CoreTop.ngd
20 map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf
21
22CoreTop.ncd: CoreTop_map.ncd
23 par -w -ol std -t 1 CoreTop_map.ncd CoreTop.ncd CoreTop.pcf
24
25CoreTop.twr: CoreTop_map.ncd
26 trce -e 3 -s 5 -xml CoreTop CoreTop.ncd -o CoreTop.twr CoreTop.pcf -ucf CoreTop.ucf
27
28CoreTop.bit: CoreTop.ut CoreTop.ncd
29 bitgen -f CoreTop.ut CoreTop.ncd
7028b02c 30
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31netgen/par/CoreTop_timesim.v: CoreTop.twr CoreTop.ncd
32 netgen -ise FPGABoy.ise -s 5 -pcf CoreTop.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim CoreTop.ncd CoreTop_timesim.v
33
34netgen/par/.CoreTop_timesim.v_work: netgen/par/CoreTop_timesim.v
35 vlogcomp netgen/par/CoreTop_timesim.v
36 vlogcomp /home/joshua/projects/fpga/ise/Xilinx101/verilog/src/glbl.v
37
38CoreTop_isim_par.exe: netgen/par/.CoreTop_timesim.v_work
39 fuse -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o CoreTop_isim_par.exe netgen/par/CoreTop_timesim.v -top CoreTop -top glbl
40
41parsim: CoreTop_isim_par.exe
42
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43%.o: %.asm
44 rgbasm -o$@ $<
7028b02c 45
922655dd 46%.bin: %.o
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47 echo "[Objects]" > tmp.lnk
48 echo $< >> tmp.lnk
49 echo "" >> tmp.lnk
50 echo "[Output]" >> tmp.lnk
51 echo $@ >> tmp.lnk
52 xlink tmp.lnk
53 rm tmp.lnk
7028b02c 54
2b7d78b5 55%.mem: %.bin mashrom
5bac4cf0 56 ./mashrom < $< > $@
7028b02c 57
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58CoreTop_%.bit: %.mem CoreTop.bit foo_bd.bmm
59 data2mem -bm foo_bd.bmm -bd $< -bt CoreTop.bit -o b $@
7028b02c 60
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61CoreTop_%.svf: CoreTop_%.bit impact.cmd
62 sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
63 impact -batch tmp.cmd
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64
65parsim: CoreTop
66
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