Dual bus processor

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 1182b327709e7d4cd3fc24e52fd2a128cd46d1c1..ec882da4d7841ee789180cd0ea85138843cfbc95 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -146,9 +146,12 @@
 
 module GBZ80Core(
        input clk,
 
 module GBZ80Core(
        input clk,

-       output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
-       inout [7:0] busdata,
-       output reg buswr, output reg busrd,
+       inout [15:0] bus0address,       /* BUS_* is latched on STATE_FETCH. */
+       inout [7:0] bus0data,
+       inout bus0wr, bus0rd,
+       inout [15:0] bus1address,       /* BUS_* is latched on STATE_FETCH. */
+       inout [7:0] bus1data,
+       inout bus1wr, bus1rd,

        input irq, input [7:0] jaddr,
        output reg [1:0] state);
 
        input irq, input [7:0] jaddr,
        output reg [1:0] state);
 


@@ -167,7 +170,24 @@ module GBZ80Core(
        reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
        
        reg [7:0] buswdata;
        reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
        
        reg [7:0] buswdata;

-       assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
+       wire [7:0] busdata;
+       
+       reg [15:0] busaddress;
+       reg buswr, busrd;
+       
+       reg bootstrap_enb;
+       
+       wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF));  /* 0 or 1 depending on which bus */
+               
+       assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz;
+       assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz;
+       assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz;
+       assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz;
+       assign busdata = (bus == 0) ? bus0data : bus1data;
+       assign bus0rd = (bus == 0) ? busrd : 1'bz;
+       assign bus1rd = (bus == 1) ? busrd : 1'bz;
+       assign bus0wr = (bus == 0) ? buswr : 1'bz;
+       assign bus1wr = (bus == 1) ? buswr : 1'bz;

 
        reg ie, iedelay;
 
 
        reg ie, iedelay;
 


@@ -257,6 +277,7 @@ module GBZ80Core(
                state <= `STATE_WRITEBACK;
                cycle <= 0;
                twobyte <= 0;
                state <= `STATE_WRITEBACK;
                cycle <= 0;
                twobyte <= 0;

+               bootstrap_enb <= 1;

        end
 
        always @(posedge clk)
        end
 
        always @(posedge clk)

diff --git a/Makefile b/Makefile
index 3a508aeb5569d47d0600a05083c35a497c344856..4b401d00d0614009ac81ffa127683f7e8013ce70 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -10,15 +10,15 @@ VLOGS_ALL = $(VLOGS) insn_call-callcc.v insn_incdec16.v insn_jr-jrcc.v \
        insn_ldm8_a.v insn_ldm16_a.v insn_ldbcde_a.v insn_alu_ext.v \
        insn_bit.v insn_two_byte.v insn_incdec_reg8.v
 
        insn_ldm8_a.v insn_ldm16_a.v insn_ldbcde_a.v insn_alu_ext.v \
        insn_bit.v insn_two_byte.v insn_incdec_reg8.v
 

-all: CoreTop_rom.svf CoreTop_diag.svf CoreTop_bootrom.svf CoreTop.twr
+all: CoreTop.svf CoreTop.twr

 
 sim: CoreTop_isim.exe
 
 
 sim: CoreTop_isim.exe
 

-CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS_ALL)
+CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS_ALL) rom.mem

        xst -ifn CoreTop.xst -ofn CoreTop.syr
 
 CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf
        xst -ifn CoreTop.xst -ofn CoreTop.syr
 
 CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf

-       ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -bm "foo.bmm" -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd
+       ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd

 
 CoreTop_map.ncd: CoreTop.ngd
        map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf
 
 CoreTop_map.ncd: CoreTop.ngd
        map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf


@@ -63,10 +63,7 @@ parsim: CoreTop_isim_par.exe
 %.mem: %.bin mashrom
        ./mashrom < $< > $@
 
 %.mem: %.bin mashrom
        ./mashrom < $< > $@
 

-CoreTop_%.bit: %.mem CoreTop.bit foo_bd.bmm
-       data2mem -bm foo_bd.bmm -bd $< -bt CoreTop.bit -o b $@
-
-CoreTop_%.svf: CoreTop_%.bit impact.cmd
+CoreTop.svf: CoreTop.bit impact.cmd

        sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
        impact -batch tmp.cmd
 
        sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
        impact -batch tmp.cmd
 

diff --git a/System.v b/System.v
index cdcee0932cbac023673f7266f2c0f3611e805211..4c5f85b140bd6291775447bbe18128950e6b7596 100644 (file)
--- a/System.v
+++ b/System.v
@@ -6,16 +6,30 @@ module ROM(
        input clk,
        input wr, rd);
 
        input clk,
        input wr, rd);
 

+       // synthesis attribute ram_style of rom is block

        reg [7:0] rom [1023:0];
        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;
        wire [7:0] odata = rom[address[10:0]];
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        reg [7:0] rom [1023:0];
        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;
        wire [7:0] odata = rom[address[10:0]];
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;

-       //assign data = rd ? odata : 8'bzzzzzzzz;

 endmodule
 
 endmodule
 

-module MiniRAM(                        /* XXX will need to go INSIDE the CPU for when we do DMA */
+module BootstrapROM(
+       input [15:0] address,
+       inout [7:0] data,
+       input clk,
+       input wr, rd);
+
+       reg [7:0] rom [255:0];
+       initial $readmemh("bootstrap.hex", rom);
+
+       wire decode = address[15:8] == 0;
+       wire [7:0] odata = rom[address[7:0]];
+       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+endmodule
+
+module MiniRAM(

        input [15:0] address,
        inout [7:0] data,
        input clk,
        input [15:0] address,
        inout [7:0] data,
        input clk,


@@ -125,9 +139,9 @@ module CoreTop(
        pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
 `endif
 
        pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
 `endif
 

-       wire [15:0] addr;       
-       wire [7:0] data;
-       wire wr, rd;
+       wire [15:0] addr [1:0];
+       wire [7:0] data [1:0];
+       wire wr [1:0], rd [1:0];

        
        wire irq, tmrirq, lcdcirq, vblankirq;
        wire [7:0] jaddr;
        
        wire irq, tmrirq, lcdcirq, vblankirq;
        wire [7:0] jaddr;


@@ -135,31 +149,42 @@ module CoreTop(
        
        GBZ80Core core(
                .clk(clk),
        
        GBZ80Core core(
                .clk(clk),

-               .busaddress(addr),
-               .busdata(data),
-               .buswr(wr),
-               .busrd(rd),
+               .bus0address(addr[0]),
+               .bus0data(data[0]),
+               .bus0wr(wr[0]),
+               .bus0rd(rd[0]),
+               .bus1address(addr[1]),
+               .bus1data(data[1]),
+               .bus1wr(wr[1]),
+               .bus1rd(rd[1]),

                .irq(irq),
                .jaddr(jaddr),
                .state(state));
        
                .irq(irq),
                .jaddr(jaddr),
                .state(state));
        

+       BootstrapROM brom(
+               .address(addr[1]),
+               .data(data[1]),
+               .clk(clk),
+               .wr(wr[1]),
+               .rd(rd[1]));
+       

        ROM rom(
        ROM rom(

-               .address(addr),
-               .data(data),
+               .address(addr[0]),
+               .data(data[0]),

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd));
+               .wr(wr[0]),
+               .rd(rd[0]));

        
        wire lcdhs, lcdvs, lcdclk;
        wire [2:0] lcdr, lcdg;
        wire [1:0] lcdb;
        
        LCDC lcdc(
        
        wire lcdhs, lcdvs, lcdclk;
        wire [2:0] lcdr, lcdg;
        wire [1:0] lcdb;
        
        LCDC lcdc(

-               .addr(addr),
-               .data(data),

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),

                .lcdcirq(lcdcirq),
                .vblankirq(vblankirq),
                .lcdclk(lcdclk),
                .lcdcirq(lcdcirq),
                .vblankirq(vblankirq),
                .lcdclk(lcdclk),


@@ -184,8 +209,8 @@ module CoreTop(
                .vgab(b));
        
        AddrMon amon(
                .vgab(b));
        
        AddrMon amon(

-               .addr(addr), 

                .clk(clk), 
                .clk(clk), 

+               .addr(addr[0]),

                .digit(digits), 
                .out(seven),
                .freeze(buttons[0]),
                .digit(digits), 
                .out(seven),
                .freeze(buttons[0]),


@@ -196,55 +221,55 @@ module CoreTop(
                                           4'b0100) );
         
        Switches sw(
                                           4'b0100) );
         
        Switches sw(

-               .address(addr),
-               .data(data),

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd),
+               .address(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),

                .ledout(leds),
                .switches(switches)
                );
 
        UART nouart (   /* no u */
                .ledout(leds),
                .switches(switches)
                );
 
        UART nouart (   /* no u */

-               .clk(clk), 
-               .wr(wr), 
-               .rd(rd), 
-               .addr(addr), 
-               .data(data), 
+               .clk(clk),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),

                .serial(serio)
                );
 
        InternalRAM ram(
                .serial(serio)
                );
 
        InternalRAM ram(

-               .address(addr),
-               .data(data),

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd)
+               .address(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0])

                );
        
        MiniRAM mram(
                );
        
        MiniRAM mram(

-               .address(addr),
-               .data(data),

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd)
+               .address(addr[1]),
+               .data(data[1]),
+               .wr(wr[1]),
+               .rd(rd[1])

                );
 
        Timer tmr(
                .clk(clk),
                );
 
        Timer tmr(
                .clk(clk),

-               .wr(wr),
-               .rd(rd),
-               .addr(addr),
-               .data(data),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),

                .irq(tmrirq)
                );
        
        Interrupt intr(
                .clk(clk),
                .irq(tmrirq)
                );
        
        Interrupt intr(
                .clk(clk),

-               .rd(rd),
-               .wr(wr),
-               .addr(addr),
-               .data(data),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),

                .vblank(vblankirq),
                .lcdc(lcdcirq),
                .tovf(tmrirq),
                .vblank(vblankirq),
                .lcdc(lcdcirq),
                .tovf(tmrirq),


@@ -255,90 +280,10 @@ module CoreTop(
        
        Soundcore sound(
                .core_clk(clk),
        
        Soundcore sound(
                .core_clk(clk),

-               .rd(rd),
-               .wr(wr),
-               .addr(addr),
-               .data(data),
+               .addr(addr[0]),
+               .data(data[0]),
+               .rd(rd[0]),
+               .wr(wr[0]),

                .snd_data_l(soundl),
                .snd_data_r(soundr));
 endmodule
                .snd_data_l(soundl),
                .snd_data_r(soundr));
 endmodule

-
-`ifdef verilator
-`else
-module TestBench();
-       reg clk = 1;
-       wire [15:0] addr;
-       wire [7:0] data;
-       wire wr, rd;
-       
-       wire irq, tmrirq;
-       wire [7:0] jaddr;
-       
-       wire [7:0] leds;
-       wire [7:0] switches;
-       
-       always #62 clk <= ~clk;
-       GBZ80Core core(
-               .clk(clk),
-               .busaddress(addr),
-               .busdata(data),
-               .buswr(wr),
-               .busrd(rd),
-               .irq(irq),
-               .jaddr(jaddr));
-       
-       ROM rom(
-               .clk(clk),
-               .address(addr),
-               .data(data),
-               .wr(wr),
-               .rd(rd));
-       
-       InternalRAM ram(
-               .address(addr),
-               .data(data),
-               .clk(clk),
-               .wr(wr),
-               .rd(rd));
-
-       wire serio;
-       UART uart(
-               .addr(addr),
-               .data(data),
-               .clk(clk),
-               .wr(wr),
-               .rd(rd),
-               .serial(serio));
-       
-       Timer tmr(
-               .clk(clk),
-               .wr(wr),
-               .rd(rd),
-               .addr(addr),
-               .data(data),
-               .irq(tmrirq));
-       
-       Interrupt intr(
-               .clk(clk),
-               .rd(rd),
-               .wr(wr),
-               .addr(addr),
-               .data(data),
-               .vblank(0),
-               .lcdc(0),
-               .tovf(tmrirq),
-               .serial(0),
-               .buttons(0),
-               .master(irq),
-               .jaddr(jaddr));
-       
-       Switches sw(
-               .clk(clk),
-               .address(addr),
-               .data(data),
-               .wr(wr),
-               .rd(rd),
-               .switches(switches),
-               .ledout(leds));
-endmodule
-`endif

diff --git a/oldrom.asm b/oldrom.asm
new file mode 100644 (file)
index 0000000..1504c71
--- /dev/null
+++ b/oldrom.asm
@@ -0,0 +1,70 @@
+       SECTION "a",HOME
+
+main:
+       ld a, $FF       ; Note that we are alive.
+       ld [$FF51],a
+       
+       ld sp, $DFF0
+       
+       ld hl, $DF81
+       ld a, $80
+       ld [hl], a
+
+       ld c, $07
+       ld a, $04       ;start timer, 4.096KHz
+       ld [c], a
+;diqs: ei
+;      ld a, $80
+;      ld c, $51
+;      ld [c], a
+;      jr diqs
+       call irqhand
+       ei
+coqs: jr coqs
+
+       section "Diq", HOME[$38]
+fuqed:
+       di
+       jr fuqed
+
+       section "fuq",HOME[$100]
+irqhand:
+       PUSH AF
+       PUSH BC
+       PUSH DE
+       PUSH HL
+       
+       xor a
+       ld c, $0F       ; ack the irq
+       ld [c], a
+       
+       ld a, $41       ; print A
+       call putc
+       
+       ld hl, $DF81
+       inc [hl]
+       ld a, [hl]
+       ld c, $51
+       ld [c], a
+
+
+       POP HL
+       POP DE
+       POP BC
+       POP AF
+       RETI
+       db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
+       db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
+       db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
+
+putc:
+       ld b, 0
+       ld c, $50
+       push af
+.waitport:
+       ld a,[c]
+       cp b
+       jr nz,.waitport
+       pop af
+       ld [c],a
+       ret

diff --git a/rom.asm b/rom.asm
deleted file mode 100644 (file)
index 1504c7199bf681185a2d1d2f8422b4c3909153eb..0000000000000000000000000000000000000000
--- a/rom.asm
+++ /dev/null
@@ -1,70 +0,0 @@
-       SECTION "a",HOME
-
-main:
-       ld a, $FF       ; Note that we are alive.
-       ld [$FF51],a
-       
-       ld sp, $DFF0
-       
-       ld hl, $DF81
-       ld a, $80
-       ld [hl], a
-
-       ld c, $07
-       ld a, $04       ;start timer, 4.096KHz
-       ld [c], a
-;diqs: ei
-;      ld a, $80
-;      ld c, $51
-;      ld [c], a
-;      jr diqs
-       call irqhand
-       ei
-coqs: jr coqs
-
-       section "Diq", HOME[$38]
-fuqed:
-       di
-       jr fuqed
-
-       section "fuq",HOME[$100]
-irqhand:
-       PUSH AF
-       PUSH BC
-       PUSH DE
-       PUSH HL
-       
-       xor a
-       ld c, $0F       ; ack the irq
-       ld [c], a
-       
-       ld a, $41       ; print A
-       call putc
-       
-       ld hl, $DF81
-       inc [hl]
-       ld a, [hl]
-       ld c, $51
-       ld [c], a
-
-
-       POP HL
-       POP DE
-       POP BC
-       POP AF
-       RETI
-       db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
-       db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
-       db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
-
-putc:
-       ld b, 0
-       ld c, $50
-       push af
-.waitport:
-       ld a,[c]
-       cp b
-       jr nz,.waitport
-       pop af
-       ld [c],a
-       ret

diff --git a/rom.asm b/rom.asm
new file mode 120000 (symlink)
index 0000000000000000000000000000000000000000..2dfb2b315e3906490c3ec90284560b1b41a4c828
--- /dev/null
+++ b/rom.asm
@@ -0,0 +1 @@
+bootrom.asm
\ No newline at end of file