[fpgaboy.git] / System.v

`timescale 1ns / 1ps
module ROM(
        input [15:0] address,
        inout [7:0] data,
        input clk,
        input wr, rd);

        reg [7:0] rom [1023:0];
        initial $readmemh("rom.hex", rom);

        wire decode = address[15:13] == 0;
        wire [7:0] odata = rom[address[10:0]];
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        //assign data = rd ? odata : 8'bzzzzzzzz;
endmodule

module MiniRAM(                 /* XXX will need to go INSIDE the CPU for when we do DMA */
        input [15:0] address,
        inout [7:0] data,
        input clk,
        input wr, rd);
        
        reg [7:0] ram [127:0];
        
        wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
        begin
                if (decode)     // This has to go this way. The only way XST knows how to do
                begin                           // block ram is chip select, write enable, and always
                        if (wr)         // reading. "else if rd" does not cut it ...
                                ram[address[6:0]] <= data;
                        odata <= ram[address[6:0]];
                end
        end
endmodule

module InternalRAM(
        input [15:0] address,
        inout [7:0] data,
        input clk,
        input wr, rd);
        
        // synthesis attribute ram_style of ram is block
        reg [7:0] ram [8191:0];
        
        wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
        begin
                if (decode)     // This has to go this way. The only way XST knows how to do
                begin                           // block ram is chip select, write enable, and always
                        if (wr)         // reading. "else if rd" does not cut it ...
                                ram[address[12:0]] <= data;
                        odata <= ram[address[12:0]];
                end
        end
endmodule

module Switches(
        input [15:0] address,
        inout [7:0] data,
        input clk,
        input wr, rd,
        input [7:0] switches,
        output reg [7:0] ledout = 0);
        
        wire decode = address == 16'hFF51;
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
        begin
                if (decode && rd)
                        odata <= switches;
                else if (decode && wr)
                        ledout <= data;
        end
endmodule

`ifdef isim
module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
endmodule
`endif

module CoreTop(
`ifdef isim
        output reg vgaclk = 0,
        output reg clk = 0,
`else
        input xtal,
        input [7:0] switches,
        input [3:0] buttons,
        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,
        output wire [7:0] seven,
`endif
        output wire hs, vs,
        output wire [2:0] r, g,
        output wire [1:0] b,
        output wire soundl, soundr);

`ifdef isim
        always #62 clk <= ~clk;
        always #100 vgaclk <= ~vgaclk;
        
        Dumpable dump(r,g,b,hs,vs,vgaclk);
        
        wire [7:0] leds;
        wire serio;
        wire [3:0] digits;
        wire [7:0] seven;
        wire [7:0] switches = 8'b0;
        wire [3:0] buttons = 4'b0;
`else   
        wire xtalb, clk, vgaclk;
        IBUFG iclkbuf(.O(xtalb), .I(xtal));
        CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
        pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
`endif

        wire [15:0] addr;       
        wire [7:0] data;
        wire wr, rd;
        
        wire irq, tmrirq, lcdcirq, vblankirq;
        wire [7:0] jaddr;
        wire [1:0] state;
        
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
                .busrd(rd),
                .irq(irq),
                .jaddr(jaddr),
                .state(state));
        
        ROM rom(
                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
                .rd(rd));
        
        wire lcdhs, lcdvs, lcdclk;
        wire [2:0] lcdr, lcdg;
        wire [1:0] lcdb;
        
        LCDC lcdc(
                .addr(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
                .rd(rd),
                .lcdcirq(lcdcirq),
                .vblankirq(vblankirq),
                .lcdclk(lcdclk),
                .lcdhs(lcdhs),
                .lcdvs(lcdvs),
                .lcdr(lcdr),
                .lcdg(lcdg),
                .lcdb(lcdb));
        
        Framebuffer fb(
                .lcdclk(lcdclk),
                .lcdhs(lcdhs),
                .lcdvs(lcdvs),
                .lcdr(lcdr),
                .lcdg(lcdg),
                .lcdb(lcdb),
                .vgaclk(vgaclk),
                .vgahs(hs),
                .vgavs(vs),
                .vgar(r),
                .vgag(g),
                .vgab(b));
        
        AddrMon amon(
                .addr(addr), 
                .clk(clk), 
                .digit(digits), 
                .out(seven),
                .freeze(buttons[0]),
                .periods(
                        (state == 2'b00) ? 4'b0010 :
                        (state == 2'b01) ? 4'b0001 :
                        (state == 2'b10) ? 4'b1000 :
                                           4'b0100) );
         
        Switches sw(
                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
                .rd(rd),
                .ledout(leds),
                .switches(switches)
                );

        UART nouart (   /* no u */
                .clk(clk), 
                .wr(wr), 
                .rd(rd), 
                .addr(addr), 
                .data(data), 
                .serial(serio)
                );

        InternalRAM ram(
                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
                .rd(rd)
                );
        
        MiniRAM mram(
                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
                .rd(rd)
                );

        Timer tmr(
                .clk(clk),
                .wr(wr),
                .rd(rd),
                .addr(addr),
                .data(data),
                .irq(tmrirq)
                );
        
        Interrupt intr(
                .clk(clk),
                .rd(rd),
                .wr(wr),
                .addr(addr),
                .data(data),
                .vblank(vblankirq),
                .lcdc(lcdcirq),
                .tovf(tmrirq),
                .serial(1'b0),
                .buttons(1'b0),
                .master(irq),
                .jaddr(jaddr));
        
        Soundcore sound(
                .core_clk(clk),
                .rd(rd),
                .wr(wr),
                .addr(addr),
                .data(data),
                .snd_data_l(soundl),
                .snd_data_r(soundr));
endmodule

`ifdef verilator
`else
module TestBench();
        reg clk = 1;
        wire [15:0] addr;
        wire [7:0] data;
        wire wr, rd;
        
        wire irq, tmrirq;
        wire [7:0] jaddr;
        
        wire [7:0] leds;
        wire [7:0] switches;
        
        always #62 clk <= ~clk;
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
                .busrd(rd),
                .irq(irq),
                .jaddr(jaddr));
        
        ROM rom(
                .clk(clk),
                .address(addr),
                .data(data),
                .wr(wr),
                .rd(rd));
        
        InternalRAM ram(
                .address(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
                .rd(rd));

        wire serio;
        UART uart(
                .addr(addr),
                .data(data),
                .clk(clk),
                .wr(wr),
                .rd(rd),
                .serial(serio));
        
        Timer tmr(
                .clk(clk),
                .wr(wr),
                .rd(rd),
                .addr(addr),
                .data(data),
                .irq(tmrirq));
        
        Interrupt intr(
                .clk(clk),
                .rd(rd),
                .wr(wr),
                .addr(addr),
                .data(data),
                .vblank(0),
                .lcdc(0),
                .tovf(tmrirq),
                .serial(0),
                .buttons(0),
                .master(irq),
                .jaddr(jaddr));
        
        Switches sw(
                .clk(clk),
                .address(addr),
                .data(data),
                .wr(wr),
                .rd(rd),
                .switches(switches),
                .ledout(leds));
endmodule
`endif