Start changing things to happen on posedge clock.

diff --git a/7seg.v b/7seg.v
index ba988b0603de51e22a7cd08d1d71b04a4a6ff3fc..11e26d40848b75e4887ee78c1db6979411c465f9 100644 (file)
--- a/7seg.v
+++ b/7seg.v
@@ -25,7 +25,7 @@ module AddrMon(
                          (dcount == 2'b10) ? periods[2] :
                                              periods[3]) };
 
-       always @ (negedge clk) begin
+       always @ (posedge clk) begin
                if (clkdv == 31) begin
                        clkdv <= 0;
                        dcount <= dcount + 1;

diff --git a/Interrupt.v b/Interrupt.v
index 1450b2cfd0b6ecf8c61e76f7ab8894cc96a3efe4..fcc396b109769355e31e6105eb82cf4b7429ae75 100644 (file)
--- a/Interrupt.v
+++ b/Interrupt.v
@@ -34,7 +34,7 @@ module Interrupt(
                       imasked[3] ? 8'h58 :
                       imasked[4] ? 8'h60 : 8'h00;
 
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (wr && (addr == `ADDR_IF || addr == `ADDR_IE)) begin
                        case(addr)

diff --git a/Sound1.v b/Sound1.v
index 41abaa539e844f84f72d0cf890a45297b8450a4b..21b1dec2c36ef924c94a7e55ee7a85ebdb1b300e 100644 (file)
--- a/Sound1.v
+++ b/Sound1.v
@@ -34,7 +34,7 @@ module Sound1(
                         addr == `ADDR_NR14 ? nr14 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
                if(en && wr) begin
                        case(addr)
                        `ADDR_NR10: nr10 <= data;

diff --git a/Sound2.v b/Sound2.v
index 2bb959861dcd9f5ebf48bc64b4bda1e02b490e63..cf8e83a72feb2952f18339bd82841db024d049da 100644 (file)
--- a/Sound2.v
+++ b/Sound2.v
@@ -32,7 +32,7 @@ module Sound2(
                         addr == `ADDR_NR24 ? nr24 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
                if(en && wr) begin
                        case(addr)
                        `ADDR_NR21: nr21 <= data;

diff --git a/Soundcore.v b/Soundcore.v
index 7752317f9e461e74f430c23cd7c37697a1146efd..626001ddd31b6050dec257a75372bb171a8baa35 100644 (file)
--- a/Soundcore.v
+++ b/Soundcore.v
@@ -36,7 +36,7 @@ module Soundcore(
                         addr == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
                if(wr) begin
                        case(addr)
                        `ADDR_NR50: nr50 <= data;

diff --git a/System.v b/System.v
index 4c5f85b140bd6291775447bbe18128950e6b7596..8f54685cfd33045ea6ad52b80f155b379a17099e 100644 (file)
--- a/System.v
+++ b/System.v
@@ -41,7 +41,7 @@ module MiniRAM(
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (decode)     // This has to go this way. The only way XST knows how to do
                begin                           // block ram is chip select, write enable, and always
@@ -65,7 +65,7 @@ module InternalRAM(
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (decode)     // This has to go this way. The only way XST knows how to do
                begin                           // block ram is chip select, write enable, and always
@@ -88,7 +88,7 @@ module Switches(
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (decode && rd)
                        odata <= switches;

diff --git a/Timer.v b/Timer.v
index 53f392deae20118ea451112fa123cf2a83391075..e46b38bbaf937d7366c8fdb903ff84a0ce6ddeeb 100644 (file)
--- a/Timer.v
+++ b/Timer.v
@@ -33,7 +33,7 @@ module Timer(
                        (clkdv[7:0] == 8'b0) :
                     0;
 
-       always @ (negedge clk) 
+       always @ (posedge clk) 
        begin
                if(wr) begin
                        case(addr)

diff --git a/Uart.v b/Uart.v
index 1f0ae7d0d31c57fbc648a6aab693e9fbd77fc367..f9d71f4c17ef5bff177a5cd0a7b8dd0e3ce01f09 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -25,7 +25,7 @@ module UART(
        
        assign odata = have_data ? 8'b1 : 8'b0;
 
-       always @ (negedge clk)
+       always @ (posedge clk)
        begin
                /* deal with diqing */
                if(newdata) begin