7seg.v

   1 module AddrMon(
   2         input [15:0] addr,
   3         input clk,
   4         input [3:0] periods,
   5         output reg [3:0] digit,
   6         output wire [7:0] out,
   7         input freeze
   8         );
   9
  10         reg [5:0] clkdv;
  11         reg [1:0] dcount;
  12
  13         reg [15:0] latch = 0;
  14
  15         wire [3:0] curval =
  16                 (dcount == 2'b00) ? latch[3:0]  :
  17                 (dcount == 2'b01) ? latch[7:4]  :
  18                 (dcount == 2'b10) ? latch[11:8] :
  19                                     latch[15:12];
  20
  21         reg [6:0] odigit;
  22         assign out = {odigit,
  23                         ~((dcount == 2'b00) ? periods[0] :
  24                           (dcount == 2'b01) ? periods[1] :
  25                           (dcount == 2'b10) ? periods[2] :
  26                                               periods[3]) };
  27
  28         always @ (negedge clk) begin
  29                 if (clkdv == 31) begin
  30                         clkdv <= 0;
  31                         dcount <= dcount + 1;
  32
  33                         case(dcount)
  34                         2'b00: digit <= 4'b1110;
  35                         2'b01: digit <= 4'b1101;
  36                         2'b10: digit <= 4'b1011;
  37                         2'b11: digit <= 4'b0111;
  38                         endcase
  39
  40                         case(curval)
  41                                                         /* ABCDEFGP */
  42                         4'h0: odigit <= ~8'b1111110;
  43                         4'h1: odigit <= ~8'b0110000;
  44                         4'h2: odigit <= ~8'b1101101;
  45                         4'h3: odigit <= ~8'b1111001;
  46                         4'h4: odigit <= ~8'b0110011;
  47                         4'h5: odigit <= ~8'b1011011;
  48                         4'h6: odigit <= ~8'b1011111;
  49                         4'h7: odigit <= ~8'b1110000;
  50                         4'h8: odigit <= ~8'b1111111;
  51                         4'h9: odigit <= ~8'b1111011;
  52                         4'hA: odigit <= ~8'b1110111;
  53                         4'hB: odigit <= ~8'b0011111;
  54                         4'hC: odigit <= ~8'b1001110;
  55                         4'hD: odigit <= ~8'b0111101;
  56                         4'hE: odigit <= ~8'b1001111;
  57                         4'hF: odigit <= ~8'b1000111;
  58                         endcase
  59                 end else
  60                         clkdv <= clkdv + 1;
  61
  62                 if (~freeze)
  63                         latch <= addr;
  64         end
  65 endmodule