From: Joshua Wise <joshua@rebirth.joshuawise.com>
Date: Sun, 4 May 2008 07:59:43 +0000 (-0400)
Subject: Start changing things to happen on posedge clock.
X-Git-Url: http://git.joshuawise.com/fpgaboy.git/commitdiff_plain/68ce013e5fe7c5d1c4e07fe8ba1eb0ba2855b280?hp=b338a0b6419b53f5c83487d57f5c923d168ae842

Start changing things to happen on posedge clock.
---

diff --git a/7seg.v b/7seg.v
index ba988b0..11e26d4 100644
--- a/7seg.v
+++ b/7seg.v
@@ -25,7 +25,7 @@ module AddrMon(
 			  (dcount == 2'b10) ? periods[2] :
 			                      periods[3]) };
 
-	always @ (negedge clk) begin
+	always @ (posedge clk) begin
 		if (clkdv == 31) begin
 			clkdv <= 0;
 			dcount <= dcount + 1;
diff --git a/Interrupt.v b/Interrupt.v
index 1450b2c..fcc396b 100644
--- a/Interrupt.v
+++ b/Interrupt.v
@@ -34,7 +34,7 @@ module Interrupt(
 		       imasked[3] ? 8'h58 :
 		       imasked[4] ? 8'h60 : 8'h00;
 
-	always @(negedge clk)
+	always @(posedge clk)
 	begin
 		if (wr && (addr == `ADDR_IF || addr == `ADDR_IE)) begin
 			case(addr)
diff --git a/Sound1.v b/Sound1.v
index 41abaa5..21b1dec 100644
--- a/Sound1.v
+++ b/Sound1.v
@@ -34,7 +34,7 @@ module Sound1(
 	                 addr == `ADDR_NR14 ? nr14 : 8'bzzzzzzzz
 	              : 8'bzzzzzzzz;
 
-	always @ (negedge core_clk) begin
+	always @ (posedge core_clk) begin
 		if(en && wr) begin
 			case(addr)
 			`ADDR_NR10: nr10 <= data;
diff --git a/Sound2.v b/Sound2.v
index 2bb9598..cf8e83a 100644
--- a/Sound2.v
+++ b/Sound2.v
@@ -32,7 +32,7 @@ module Sound2(
 	                 addr == `ADDR_NR24 ? nr24 : 8'bzzzzzzzz
 	              : 8'bzzzzzzzz;
 
-	always @ (negedge core_clk) begin
+	always @ (posedge core_clk) begin
 		if(en && wr) begin
 			case(addr)
 			`ADDR_NR21: nr21 <= data;
diff --git a/Soundcore.v b/Soundcore.v
index 7752317..626001d 100644
--- a/Soundcore.v
+++ b/Soundcore.v
@@ -36,7 +36,7 @@ module Soundcore(
 	                 addr == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
 		      : 8'bzzzzzzzz;
 
-	always @ (negedge core_clk) begin
+	always @ (posedge core_clk) begin
 		if(wr) begin
 			case(addr)
 			`ADDR_NR50: nr50 <= data;
diff --git a/System.v b/System.v
index 4c5f85b..8f54685 100644
--- a/System.v
+++ b/System.v
@@ -41,7 +41,7 @@ module MiniRAM(
 	reg [7:0] odata;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
-	always @(negedge clk)
+	always @(posedge clk)
 	begin
 		if (decode)	// This has to go this way. The only way XST knows how to do
 		begin				// block ram is chip select, write enable, and always
@@ -65,7 +65,7 @@ module InternalRAM(
 	reg [7:0] odata;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
-	always @(negedge clk)
+	always @(posedge clk)
 	begin
 		if (decode)	// This has to go this way. The only way XST knows how to do
 		begin				// block ram is chip select, write enable, and always
@@ -88,7 +88,7 @@ module Switches(
 	reg [7:0] odata;
 	assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 	
-	always @(negedge clk)
+	always @(posedge clk)
 	begin
 		if (decode && rd)
 			odata <= switches;
diff --git a/Timer.v b/Timer.v
index 53f392d..e46b38b 100644
--- a/Timer.v
+++ b/Timer.v
@@ -33,7 +33,7 @@ module Timer(
 	                (clkdv[7:0] == 8'b0) :
 	             0;
 
-	always @ (negedge clk) 
+	always @ (posedge clk) 
 	begin
 		if(wr) begin
 			case(addr)
diff --git a/Uart.v b/Uart.v
index 1f0ae7d..f9d71f4 100644
--- a/Uart.v
+++ b/Uart.v
@@ -25,7 +25,7 @@ module UART(
 	
 	assign odata = have_data ? 8'b1 : 8'b0;
 
-	always @ (negedge clk)
+	always @ (posedge clk)
 	begin
 		/* deal with diqing */
 		if(newdata) begin