address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
wdata <= registers[`REG_PCH];
wr <= 1;
end
address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
wdata <= registers[`REG_PCH];
wr <= 1;
end
address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
wdata <= registers[`REG_PCL];
wr <= 1;
end
address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
wdata <= registers[`REG_PCL];
wr <= 1;
end
end
5: begin
{registers[`REG_SPH],registers[`REG_SPL]} <=
{registers[`REG_SPH],registers[`REG_SPL]} - 2;
end
5: begin
{registers[`REG_SPH],registers[`REG_SPL]} <=
{registers[`REG_SPH],registers[`REG_SPL]} - 2;