Update the 7seg more often.
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Fri, 4 Apr 2008 03:52:44 +0000 (23:52 -0400)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Fri, 4 Apr 2008 03:52:44 +0000 (23:52 -0400)
7seg.v
FPGABoy.ise

diff --git a/7seg.v b/7seg.v
index ed4519a..8e91b03 100644 (file)
--- a/7seg.v
+++ b/7seg.v
@@ -6,7 +6,7 @@ module AddrMon(
        input freeze
        );
 
-       reg [12:0] clkdv;
+       reg [10:0] clkdv;
        reg [1:0] dcount;
        
        reg [15:0] latch = 0;
@@ -24,7 +24,7 @@ module AddrMon(
                        latch <= addr;
        end
 
-       always @ (posedge clkdv[12])
+       always @ (posedge clkdv[10])
        begin
                dcount <= dcount + 1;
 
index cf8e697..bd62a30 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ
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