Update the 7seg more often.
[fpgaboy.git] / 7seg.v
1 module AddrMon(
2         input [15:0] addr,
3         input clk,
4         output reg [3:0] digit,
5         output reg [7:0] out,
6         input freeze
7         );
8
9         reg [10:0] clkdv;
10         reg [1:0] dcount;
11         
12         reg [15:0] latch = 0;
13
14         wire [3:0] curval =
15                 (dcount == 2'b00) ? latch[3:0]  :
16                 (dcount == 2'b01) ? latch[7:4]  :
17                 (dcount == 2'b10) ? latch[11:8] :
18                                      latch[15:12];
19
20         always @ (negedge clk)
21         begin
22                 clkdv <= clkdv + 1;
23                 if (~freeze)
24                         latch <= addr;
25         end
26
27         always @ (posedge clkdv[10])
28         begin
29                 dcount <= dcount + 1;
30
31                 case(dcount)
32                 2'b00: digit <= 4'b1110;
33                 2'b01: digit <= 4'b1101;
34                 2'b10: digit <= 4'b1011;
35                 2'b11: digit <= 4'b0111;
36                 endcase
37
38                 case(curval)
39                              /* ABCDEFGP */
40                 4'h0: out <= ~8'b11111100;
41                 4'h1: out <= ~8'b01100000;
42                 4'h2: out <= ~8'b11011010;
43                 4'h3: out <= ~8'b11110010;
44                 4'h4: out <= ~8'b01100110;
45                 4'h5: out <= ~8'b10110110;
46                 4'h6: out <= ~8'b10111110;
47                 4'h7: out <= ~8'b11100000;
48                 4'h8: out <= ~8'b11111110;
49                 4'h9: out <= ~8'b11110110;
50                 4'hA: out <= ~8'b11101110;
51                 4'hB: out <= ~8'b00111110;
52                 4'hC: out <= ~8'b10011100;
53                 4'hD: out <= ~8'b01111010;
54                 4'hE: out <= ~8'b10011110;
55                 4'hF: out <= ~8'b10001110;
56                 endcase
57         end
58 endmodule
This page took 0.019974 seconds and 4 git commands to generate.