Update the 7seg more often.

diff --git a/7seg.v b/7seg.v
index ed4519ade9d34ac4c87c33c9135a0a180769f6d7..8e91b038669690cbb954c8f7178d602cda72eb30 100644 (file)
--- a/7seg.v
+++ b/7seg.v
@@ -6,7 +6,7 @@ module AddrMon(
        input freeze
        );
 
        input freeze
        );
 

-       reg [12:0] clkdv;
+       reg [10:0] clkdv;

        reg [1:0] dcount;
        
        reg [15:0] latch = 0;
        reg [1:0] dcount;
        
        reg [15:0] latch = 0;


@@ -24,7 +24,7 @@ module AddrMon(
                        latch <= addr;
        end
 
                        latch <= addr;
        end
 

-       always @ (posedge clkdv[12])
+       always @ (posedge clkdv[10])

        begin
                dcount <= dcount + 1;
 
        begin
                dcount <= dcount + 1;
 

diff --git a/FPGABoy.ise b/FPGABoy.ise
index cf8e69757eb987a5c3ebe3abcf10e59e3e11d6a1..bd62a309e2a75734319bf062991e4df87f6bf1b8 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ