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Wire switches back up and remove cclk.
[fpgaboy.git] / insn_alu8.v
1 `ifdef EXECUTE
2         `INSN_ALU8: begin
3                 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
4                         `EXEC_READ(`_HL)
5                 else begin
6                         `EXEC_NEWCYCLE
7                         `EXEC_INC_PC
8                         case (opcode[2:0])
9                         `INSN_reg_A:    tmp <= `_A;
10                         `INSN_reg_B:    tmp <= `_B;
11                         `INSN_reg_C:    tmp <= `_C;
12                         `INSN_reg_D:    tmp <= `_D;
13                         `INSN_reg_E:    tmp <= `_E;
14                         `INSN_reg_H:    tmp <= `_H;
15                         `INSN_reg_L:    tmp <= `_L;
16                         `INSN_reg_dHL:  tmp <= rdata;
17                         endcase
18                 end
19         end
20 `endif
21
22 `ifdef WRITEBACK
23         `INSN_ALU8: begin
24                 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
25                         /* Sit on our asses. */
26                 end else begin          /* Actually do the computation! */
27                         case (opcode[5:3])
28                         `INSN_alu_ADD: begin
29                                 `_A <= `_A + tmp;
30                                 `_F <=  { /* Z */ ((`_A + tmp) == 0) ? 1'b1 : 1'b0,
31                                           /* N */ 1'b0,
32                                           /* H */ (({1'b0,`_A[3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
33                                           /* C */ (({1'b0,`_A} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
34                                           `_F[3:0]
35                                         };
36                         end
37                         `INSN_alu_ADC: begin
38                                 `_A <= `_A + tmp + {7'b0,`_F[4]};
39                                 `_F <=  { /* Z */ ((`_A + tmp + {7'b0,`_F[4]}) == 0) ? 1'b1 : 1'b0,
40                                           /* N */ 1'b0,
41                                           /* H */ (({1'b0,`_A[3:0]} + {1'b0,tmp[3:0]} + {4'b0,`_F[4]}) >> 4 == 1) ? 1'b1 : 1'b0,
42                                           /* C */ (({1'b0,`_A} + {1'b0,tmp} + {8'b0,`_F[4]}) >> 8 == 1) ? 1'b1 : 1'b0,
43                                           `_F[3:0]
44                                         };
45                         end
46                         `INSN_alu_SUB: begin
47                                 `_A <= `_A - tmp;
48                                 `_F <=  { /* Z */ (`_A == tmp) ? 1'b1 : 1'b0,
49                                           /* N */ 1'b1,
50                                           /* H */ (tmp[3:0] > `_A[3:0]) ? 1'b1 : 1'b0,
51                                           /* C */ (tmp > `_A) ? 1'b1 : 1'b0,
52                                           `_F[3:0]
53                                         };
54                         end
55                         `INSN_alu_SBC: begin
56                                 `_A <= `_A - (tmp + {7'b0,`_F[4]});
57                                 `_F <=  { /* Z */ ((`_A - (tmp + {7'b0,`_F[4]})) == 0) ? 1'b1 : 1'b0,
58                                           /* N */ 1'b1,
59                                           /* H */ (({1'b0,tmp[3:0]} + {4'b0,`_F[4]}) > {1'b0,`_A[3:0]}) ? 1'b1 : 1'b0,
60                                           /* C */ (({1'b0,tmp} + {8'b0,`_F[4]}) > {1'b0,`_A[7:0]}) ? 1'b1 : 1'b0,
61                                           `_F[3:0]
62                                         };
63                         end
64                         `INSN_alu_AND: begin
65                                 `_A <= `_A & tmp;
66                                 `_F <=  { /* Z */ ((`_A & tmp) == 0) ? 1'b1 : 1'b0,
67                                           3'b010,
68                                           `_F[3:0]
69                                         };
70                         end
71                         `INSN_alu_OR: begin
72                                 `_A <= `_A | tmp;
73                                 `_F <=  { /* Z */ ((`_A | tmp) == 0) ? 1'b1 : 1'b0,
74                                           3'b000,
75                                           `_F[3:0]
76                                         };
77                         end
78                         `INSN_alu_XOR: begin
79                                 `_A <= `_A ^ tmp;
80                                 `_F <=  { /* Z */ ((`_A ^ tmp) == 0) ? 1'b1 : 1'b0,
81                                           3'b000,
82                                           `_F[3:0]
83                                         };
84                         end
85                         `INSN_alu_CP: begin
86                                 `_F <=  { /* Z */ (`_A == tmp) ? 1'b1 : 1'b0,
87                                           /* N */ 1'b1,
88                                           /* H */ (tmp[3:0] > `_A[3:0]) ? 1'b1 : 1'b0,
89                                           /* C */ (tmp > `_A) ? 1'b1 : 1'b0,
90                                           `_F[3:0]
91                                         };
92                         end
93                         default:
94                                 $stop;
95                         endcase
96                 end
97         end
98 `endif
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