Wire switches back up and remove cclk.
[fpgaboy.git] / insn_alu8.v
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1`ifdef EXECUTE
2 `INSN_ALU8: begin
5509558d 3 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
5c33c5c0 4 `EXEC_READ(`_HL)
5509558d 5 else begin
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6 `EXEC_NEWCYCLE
7 `EXEC_INC_PC
3ad960bd 8 case (opcode[2:0])
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9 `INSN_reg_A: tmp <= `_A;
10 `INSN_reg_B: tmp <= `_B;
11 `INSN_reg_C: tmp <= `_C;
12 `INSN_reg_D: tmp <= `_D;
13 `INSN_reg_E: tmp <= `_E;
14 `INSN_reg_H: tmp <= `_H;
15 `INSN_reg_L: tmp <= `_L;
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16 `INSN_reg_dHL: tmp <= rdata;
17 endcase
18 end
19 end
20`endif
21
22`ifdef WRITEBACK
23 `INSN_ALU8: begin
24 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
25 /* Sit on our asses. */
26 end else begin /* Actually do the computation! */
27 case (opcode[5:3])
28 `INSN_alu_ADD: begin
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29 `_A <= `_A + tmp;
30 `_F <= { /* Z */ ((`_A + tmp) == 0) ? 1'b1 : 1'b0,
3ad960bd 31 /* N */ 1'b0,
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32 /* H */ (({1'b0,`_A[3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
33 /* C */ (({1'b0,`_A} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
34 `_F[3:0]
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35 };
36 end
37 `INSN_alu_ADC: begin
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38 `_A <= `_A + tmp + {7'b0,`_F[4]};
39 `_F <= { /* Z */ ((`_A + tmp + {7'b0,`_F[4]}) == 0) ? 1'b1 : 1'b0,
3ad960bd 40 /* N */ 1'b0,
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41 /* H */ (({1'b0,`_A[3:0]} + {1'b0,tmp[3:0]} + {4'b0,`_F[4]}) >> 4 == 1) ? 1'b1 : 1'b0,
42 /* C */ (({1'b0,`_A} + {1'b0,tmp} + {8'b0,`_F[4]}) >> 8 == 1) ? 1'b1 : 1'b0,
43 `_F[3:0]
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44 };
45 end
46 `INSN_alu_SUB: begin
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47 `_A <= `_A - tmp;
48 `_F <= { /* Z */ (`_A == tmp) ? 1'b1 : 1'b0,
3ad960bd 49 /* N */ 1'b1,
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50 /* H */ (tmp[3:0] > `_A[3:0]) ? 1'b1 : 1'b0,
51 /* C */ (tmp > `_A) ? 1'b1 : 1'b0,
52 `_F[3:0]
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53 };
54 end
55 `INSN_alu_SBC: begin
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56 `_A <= `_A - (tmp + {7'b0,`_F[4]});
57 `_F <= { /* Z */ ((`_A - (tmp + {7'b0,`_F[4]})) == 0) ? 1'b1 : 1'b0,
3ad960bd 58 /* N */ 1'b1,
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59 /* H */ (({1'b0,tmp[3:0]} + {4'b0,`_F[4]}) > {1'b0,`_A[3:0]}) ? 1'b1 : 1'b0,
60 /* C */ (({1'b0,tmp} + {8'b0,`_F[4]}) > {1'b0,`_A[7:0]}) ? 1'b1 : 1'b0,
61 `_F[3:0]
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62 };
63 end
64 `INSN_alu_AND: begin
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65 `_A <= `_A & tmp;
66 `_F <= { /* Z */ ((`_A & tmp) == 0) ? 1'b1 : 1'b0,
3ad960bd 67 3'b010,
5509558d 68 `_F[3:0]
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69 };
70 end
71 `INSN_alu_OR: begin
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72 `_A <= `_A | tmp;
73 `_F <= { /* Z */ ((`_A | tmp) == 0) ? 1'b1 : 1'b0,
3ad960bd 74 3'b000,
5509558d 75 `_F[3:0]
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76 };
77 end
78 `INSN_alu_XOR: begin
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79 `_A <= `_A ^ tmp;
80 `_F <= { /* Z */ ((`_A ^ tmp) == 0) ? 1'b1 : 1'b0,
3ad960bd 81 3'b000,
5509558d 82 `_F[3:0]
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83 };
84 end
85 `INSN_alu_CP: begin
5509558d 86 `_F <= { /* Z */ (`_A == tmp) ? 1'b1 : 1'b0,
3ad960bd 87 /* N */ 1'b1,
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88 /* H */ (tmp[3:0] > `_A[3:0]) ? 1'b1 : 1'b0,
89 /* C */ (tmp > `_A) ? 1'b1 : 1'b0,
90 `_F[3:0]
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91 };
92 end
93 default:
94 $stop;
95 endcase
96 end
97 end
98`endif
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