Finish splitting out functions.
[fpgaboy.git] / insn_alu8.v
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1`ifdef EXECUTE
2 `INSN_ALU8: begin
3 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
4 // fffffffff fuck your shit, read from (HL) :(
5 rd <= 1;
6 address <= {registers[`REG_H], registers[`REG_L]};
7 end else begin
8 `EXEC_NEWCYCLE;
9 `EXEC_INC_PC;
10 case (opcode[2:0])
11 `INSN_reg_A: tmp <= registers[`REG_A];
12 `INSN_reg_B: tmp <= registers[`REG_B];
13 `INSN_reg_C: tmp <= registers[`REG_C];
14 `INSN_reg_D: tmp <= registers[`REG_D];
15 `INSN_reg_E: tmp <= registers[`REG_E];
16 `INSN_reg_H: tmp <= registers[`REG_H];
17 `INSN_reg_L: tmp <= registers[`REG_L];
18 `INSN_reg_dHL: tmp <= rdata;
19 endcase
20 end
21 end
22`endif
23
24`ifdef WRITEBACK
25 `INSN_ALU8: begin
26 if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
27 /* Sit on our asses. */
28 end else begin /* Actually do the computation! */
29 case (opcode[5:3])
30 `INSN_alu_ADD: begin
31 registers[`REG_A] <=
32 registers[`REG_A] + tmp;
33 registers[`REG_F] <=
34 { /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
35 /* N */ 1'b0,
36 /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
37 /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
38 registers[`REG_F][3:0]
39 };
40 end
41 `INSN_alu_ADC: begin
42 registers[`REG_A] <=
43 registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
44 registers[`REG_F] <=
45 { /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
46 /* N */ 1'b0,
47 /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
48 /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
49 registers[`REG_F][3:0]
50 };
51 end
52 `INSN_alu_SUB: begin
53 registers[`REG_A] <=
54 registers[`REG_A] - tmp;
55 registers[`REG_F] <=
56 { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
57 /* N */ 1'b1,
58 /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
59 /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
60 registers[`REG_F][3:0]
61 };
62 end
63 `INSN_alu_SBC: begin
64 registers[`REG_A] <=
65 registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]});
66 registers[`REG_F] <=
67 { /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0,
68 /* N */ 1'b1,
69 /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0,
70 /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0,
71 registers[`REG_F][3:0]
72 };
73 end
74 `INSN_alu_AND: begin
75 registers[`REG_A] <=
76 registers[`REG_A] & tmp;
77 registers[`REG_F] <=
78 { /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
79 3'b010,
80 registers[`REG_F][3:0]
81 };
82 end
83 `INSN_alu_OR: begin
84 registers[`REG_A] <=
85 registers[`REG_A] | tmp;
86 registers[`REG_F] <=
87 { /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
88 3'b000,
89 registers[`REG_F][3:0]
90 };
91 end
92 `INSN_alu_XOR: begin
93 registers[`REG_A] <=
94 registers[`REG_A] ^ tmp;
95 registers[`REG_F] <=
96 { /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
97 3'b000,
98 registers[`REG_F][3:0]
99 };
100 end
101 `INSN_alu_CP: begin
102 registers[`REG_F] <=
103 { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
104 /* N */ 1'b1,
105 /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
106 /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
107 registers[`REG_F][3:0]
108 };
109 end
110 default:
111 $stop;
112 endcase
113 end
114 end
115`endif
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