Cleanups to make code nicer looking. ALU subtraction fixes.
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Sun, 6 Apr 2008 07:56:04 +0000 (03:56 -0400)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Sun, 6 Apr 2008 07:56:04 +0000 (03:56 -0400)
GBZ80Core.v
insn_alu8.v
insn_vop_intr.v

index e085739..6039b30 100644 (file)
 `define REG_PCH        10
 `define REG_PCL        11
 
+`define _A     registers[`REG_A]
+`define _B     registers[`REG_B]
+`define _C     registers[`REG_C]
+`define _D     registers[`REG_D]
+`define _E     registers[`REG_E]
+`define _F     registers[`REG_F]
+`define _H     registers[`REG_H]
+`define _L     registers[`REG_L]
+`define _SPH   registers[`REG_SPH]
+`define _SPL   registers[`REG_SPL]
+`define _PCH   registers[`REG_PCH]
+`define _PCL   registers[`REG_PCL]
+`define _AF    {`_A, `_F}
+`define _BC    {`_B, `_C}
+`define _DE    {`_D, `_E}
+`define _HL    {`_H, `_L}
+`define _SP    {`_SPH, `_SPL}
+`define _PC    {`_PCH, `_PCL}
+
 `define FLAG_Z 8'b10000000
 `define FLAG_N 8'b01000000
 `define FLAG_H 8'b00100000
 `define INSN_alu_SCF           3'b110
 `define INSN_alu_CCF           3'b111
 
+`define EXEC_INC_PC \
+       `_PC <= `_PC + 1
+`define EXEC_NEXTADDR_PCINC \
+       address <= `_PC + 1
+`define EXEC_NEWCYCLE \
+       begin newcycle <= 1; rd <= 1; wr <= 0; end
+`define EXEC_WRITE(ad, da) \
+       begin address <= (ad); \
+       wdata <= (da); \
+       wr <= 1; end
+`define EXEC_READ(ad) \
+       begin address <= (ad); \
+       rd <= 1; end
+
 module GBZ80Core(
        input clk,
        output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
@@ -184,12 +217,7 @@ module GBZ80Core(
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
-`define EXEC_INC_PC \
-       {registers[`REG_PCH], registers[`REG_PCL]} <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
-`define EXEC_NEXTADDR_PCINC \
-       address <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
-`define EXEC_NEWCYCLE \
-       newcycle <= 1; rd <= 1; wr <= 0
+
                        casex (opcode)
                        `define EXECUTE
                        `include "allinsns.v"
index 8470e27..6abcb90 100644 (file)
@@ -1,20 +1,18 @@
 `ifdef EXECUTE
        `INSN_ALU8: begin
-               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
-                       // fffffffff fuck your shit, read from (HL) :(
-                       rd <= 1;
-                       address <= {registers[`REG_H], registers[`REG_L]};
-               end else begin
+               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0))
+                       `EXEC_READ(_HL);
+               else begin
                        `EXEC_NEWCYCLE;
                        `EXEC_INC_PC;
                        case (opcode[2:0])
-                       `INSN_reg_A:    tmp <= registers[`REG_A];
-                       `INSN_reg_B:    tmp <= registers[`REG_B];
-                       `INSN_reg_C:    tmp <= registers[`REG_C];
-                       `INSN_reg_D:    tmp <= registers[`REG_D];
-                       `INSN_reg_E:    tmp <= registers[`REG_E];
-                       `INSN_reg_H:    tmp <= registers[`REG_H];
-                       `INSN_reg_L:    tmp <= registers[`REG_L];
+                       `INSN_reg_A:    tmp <= `_A;
+                       `INSN_reg_B:    tmp <= `_B;
+                       `INSN_reg_C:    tmp <= `_C;
+                       `INSN_reg_D:    tmp <= `_D;
+                       `INSN_reg_E:    tmp <= `_E;
+                       `INSN_reg_H:    tmp <= `_H;
+                       `INSN_reg_L:    tmp <= `_L;
                        `INSN_reg_dHL:  tmp <= rdata;
                        endcase
                end
                end else begin          /* Actually do the computation! */
                        case (opcode[5:3])
                        `INSN_alu_ADD: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] + tmp;
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A + tmp;
+                               `_F <=  { /* Z */ ((`_A + tmp) == 0) ? 1'b1 : 1'b0,
                                          /* N */ 1'b0,
-                                         /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-                                         /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-                                         registers[`REG_F][3:0]
+                                         /* H */ (({1'b0,`_A[3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+                                         /* C */ (({1'b0,`_A} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_ADC: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A + tmp + {7'b0,`_F[4]};
+                               `_F <=  { /* Z */ ((`_A + tmp + {7'b0,`_F[4]}) == 0) ? 1'b1 : 1'b0,
                                          /* N */ 1'b0,
-                                         /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
-                                         /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
-                                         registers[`REG_F][3:0]
+                                         /* H */ (({1'b0,`_A[3:0]} + {1'b0,tmp[3:0]} + {4'b0,`_F[4]}) >> 4 == 1) ? 1'b1 : 1'b0,
+                                         /* C */ (({1'b0,`_A} + {1'b0,tmp} + {8'b0,`_F[4]}) >> 8 == 1) ? 1'b1 : 1'b0,
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_SUB: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] - tmp;
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A - tmp;
+                               `_F <=  { /* Z */ (`_A == tmp) ? 1'b1 : 1'b0,
                                          /* N */ 1'b1,
-                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-                                         /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-                                         registers[`REG_F][3:0]
+                                         /* H */ (tmp[3:0] > `_A[3:0]) ? 1'b1 : 1'b0,
+                                         /* C */ (tmp > `_A) ? 1'b1 : 1'b0,
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_SBC: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]});
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A - (tmp + {7'b0,`_F[4]});
+                               `_F <=  { /* Z */ ((`_A - (tmp + {7'b0,`_F[4]})) == 0) ? 1'b1 : 1'b0,
                                          /* N */ 1'b1,
-                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0,
-                                         /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0,
-                                         registers[`REG_F][3:0]
+                                         /* H */ (({1'b0,tmp[3:0]} + {4'b0,`_F[4]}) > {1'b0,`_A[3:0]}) ? 1'b1 : 1'b0,
+                                         /* C */ (({1'b0,tmp} + {8'b0,`_F[4]}) > {1'b0,`_A[7:0]}) ? 1'b1 : 1'b0,
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_AND: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] & tmp;
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A & tmp;
+                               `_F <=  { /* Z */ ((`_A & tmp) == 0) ? 1'b1 : 1'b0,
                                          3'b010,
-                                         registers[`REG_F][3:0]
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_OR: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] | tmp;
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A | tmp;
+                               `_F <=  { /* Z */ ((`_A | tmp) == 0) ? 1'b1 : 1'b0,
                                          3'b000,
-                                         registers[`REG_F][3:0]
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_XOR: begin
-                               registers[`REG_A] <=
-                                       registers[`REG_A] ^ tmp;
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
+                               `_A <= `_A ^ tmp;
+                               `_F <=  { /* Z */ ((`_A ^ tmp) == 0) ? 1'b1 : 1'b0,
                                          3'b000,
-                                         registers[`REG_F][3:0]
+                                         `_F[3:0]
                                        };
                        end
                        `INSN_alu_CP: begin
-                               registers[`REG_F] <=
-                                       { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+                               `_F <=  { /* Z */ (`_A == tmp) ? 1'b1 : 1'b0,
                                          /* N */ 1'b1,
-                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-                                         /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-                                         registers[`REG_F][3:0]
+                                         /* H */ (tmp[3:0] > `_A[3:0]) ? 1'b1 : 1'b0,
+                                         /* C */ (tmp > `_A) ? 1'b1 : 1'b0,
+                                         `_F[3:0]
                                        };
                        end
                        default:
index 134d462..06218f4 100644 (file)
@@ -1,19 +1,9 @@
 `ifdef EXECUTE
        `INSN_VOP_INTR: begin
                case (cycle)
-               0:      begin
-                               address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
-                               wdata <= registers[`REG_PCH];
-                               wr <= 1;
-                       end
-               1:      begin
-                               address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
-                               wdata <= registers[`REG_PCL];
-                               wr <= 1;
-                       end
-               2:      begin
-                               `EXEC_NEWCYCLE;
-                       end
+               0:      `EXEC_WRITE(`_SP - 1, `_PCH);
+               1:      `EXEC_WRITE(`_SP - 2, `_PCL);
+               2:      `EXEC_NEWCYCLE;
                endcase
        end
 `endif
                1:      begin end
                2:      begin
                                ie <= 0;
-                               {registers[`REG_PCH],registers[`REG_PCL]} <=
-                                       {8'b0,jaddr};
-                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                       {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+                               `_PC <= {8'b0, jaddr};
+                               `_SP <= `_SP - 2;
                        end
                endcase
        end
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