system, Writeback, Memory, Execute: Only update the CPSR when an update is specified...

diff --git a/Execute.v b/Execute.v
index 65825810a42b8b468504f9af2b072d9bbc635aae..7dcc4b991d7da72df4adf9b34bfcc1a7ee61af43 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -19,6 +19,7 @@ module Execute(
        output reg outbubble = 1,
        output reg [31:0] outcpsr = 0,
        output reg [31:0] outspsr = 0,
        output reg outbubble = 1,
        output reg [31:0] outcpsr = 0,
        output reg [31:0] outspsr = 0,

+       output reg outcpsrup = 0,

        output reg write_reg = 1'bx,
        output reg [3:0] write_num = 4'bxxxx,
        output reg [31:0] write_data = 32'hxxxxxxxx,
        output reg write_reg = 1'bx,
        output reg [3:0] write_num = 4'bxxxx,
        output reg [31:0] write_data = 32'hxxxxxxxx,


@@ -42,6 +43,7 @@ module Execute(
        
        reg next_outbubble;
        reg [31:0] next_outcpsr, next_outspsr;
        
        reg next_outbubble;
        reg [31:0] next_outcpsr, next_outspsr;

+       reg next_outcpsrup;

        reg next_write_reg;
        reg [3:0] next_write_num;
 
        reg next_write_reg;
        reg [3:0] next_write_num;
 


@@ -65,6 +67,7 @@ module Execute(
                        outbubble <= next_outbubble;
                        outcpsr <= next_outcpsr;
                        outspsr <= next_outspsr;
                        outbubble <= next_outbubble;
                        outcpsr <= next_outcpsr;
                        outspsr <= next_outspsr;

+                       outcpsrup <= next_outcpsrup;

                        write_reg <= next_write_reg;
                        write_num <= next_write_num;
                        write_data <= next_write_data;
                        write_reg <= next_write_reg;
                        write_num <= next_write_num;
                        write_data <= next_write_data;


@@ -93,6 +96,7 @@ module Execute(
                next_outbubble = inbubble | flush | delayedflush;
                next_outcpsr = cpsr;
                next_outspsr = spsr;
                next_outbubble = inbubble | flush | delayedflush;
                next_outcpsr = cpsr;
                next_outspsr = spsr;

+               next_outcpsrup = 0;

                next_write_reg = 0;
                next_write_num = 4'hx;
                next_write_data = 32'hxxxxxxxx;
                next_write_reg = 0;
                next_write_num = 4'hx;
                next_write_data = 32'hxxxxxxxx;


@@ -124,6 +128,7 @@ module Execute(
                        outstall = outstall | ((!prevstall | !mult_done) && !inbubble);
                        next_outbubble = next_outbubble | !mult_done | !prevstall;
                        next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
                        outstall = outstall | ((!prevstall | !mult_done) && !inbubble);
                        next_outbubble = next_outbubble | !mult_done | !prevstall;
                        next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;

+                       next_outcpsrup = insn[20] /* S */;

                        next_write_reg = 1;
                        next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
                        next_write_data = mult_result;
                        next_write_reg = 1;
                        next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
                        next_write_data = mult_result;


@@ -137,9 +142,11 @@ module Execute(
                                next_write_data = spsr;
                        else
                                next_write_data = cpsr;
                                next_write_data = spsr;
                        else
                                next_write_data = cpsr;

+                       next_outcpsrup = 1;

                end
                `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
                `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
                end
                `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
                `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */

+               begin

                        if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))       /* flags only */
                        begin
                                if (insn[22] /* Ps */)
                        if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))       /* flags only */
                        begin
                                if (insn[22] /* Ps */)


@@ -152,6 +159,8 @@ module Execute(
                                else
                                        next_outcpsr = op0;
                        end
                                else
                                        next_outcpsr = op0;
                        end

+                       next_outcpsrup = 1;
+               end

                `DECODE_ALU_SWP,        /* Atomic swap */
                `DECODE_ALU_BX,         /* Branch */
                `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
                `DECODE_ALU_SWP,        /* Atomic swap */
                `DECODE_ALU_BX,         /* Branch */
                `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */


@@ -171,6 +180,7 @@ module Execute(
                        end
                        
                        next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
                        end
                        
                        next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;

+                       next_outcpsrup = insn[20] /* S */;

                end
                `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
                `DECODE_LDRSTR,         /* Single data transfer */
                end
                `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
                `DECODE_LDRSTR,         /* Single data transfer */

diff --git a/Memory.v b/Memory.v
index 87bc4f999b67471c743fba705aa37dea20d48ee7..7ca786e4c046aa8fc49b98f3dea20af937537911 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -36,6 +36,7 @@ module Memory(
        input [31:0] op2,
        input [31:0] spsr,
        input [31:0] cpsr,
        input [31:0] op2,
        input [31:0] spsr,
        input [31:0] cpsr,

+       input cpsrup,

        input write_reg,
        input [3:0] write_num,
        input [31:0] write_data,
        input write_reg,
        input [3:0] write_num,
        input [31:0] write_data,


@@ -49,10 +50,12 @@ module Memory(
        output reg [3:0] out_write_num = 4'bxxxx,
        output reg [31:0] out_write_data = 32'hxxxxxxxx,
        output reg [31:0] outspsr = 32'hxxxxxxxx,
        output reg [3:0] out_write_num = 4'bxxxx,
        output reg [31:0] out_write_data = 32'hxxxxxxxx,
        output reg [31:0] outspsr = 32'hxxxxxxxx,

-       output reg [31:0] outcpsr = 32'hxxxxxxxx
+       output reg [31:0] outcpsr = 32'hxxxxxxxx,
+       output reg outcpsrup = 1'hx

        );
 
        reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
        );
 
        reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;

+       reg next_outcpsrup;

        reg [31:0] prevaddr;
        reg [3:0] next_regsel, cur_reg, prev_reg;
        reg next_writeback;
        reg [31:0] prevaddr;
        reg [3:0] next_regsel, cur_reg, prev_reg;
        reg next_writeback;


@@ -92,6 +95,7 @@ module Memory(
                prev_raddr <= raddr;
                outcpsr <= next_outcpsr;
                outspsr <= spsr;
                prev_raddr <= raddr;
                outcpsr <= next_outcpsr;
                outspsr <= spsr;

+               outcpsrup <= next_outcpsrup;

                swp_state <= next_swp_state;
                lsm_state <= next_lsm_state;
                lsr_state <= next_lsr_state;
                swp_state <= next_swp_state;
                lsm_state <= next_lsm_state;
                lsr_state <= next_lsr_state;


@@ -126,6 +130,7 @@ module Memory(
                cp_write = 32'hxxxxxxxx;
                offset = prev_offset;
                next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
                cp_write = 32'hxxxxxxxx;
                offset = prev_offset;
                next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;

+               next_outcpsrup = cpsrup;

                lsrh_rddata = 32'hxxxxxxxx;
                lsrh_rddata_s1 = 16'hxxxx;
                lsrh_rddata_s2 = 8'hxx;
                lsrh_rddata = 32'hxxxxxxxx;
                lsrh_rddata_s1 = 16'hxxxx;
                lsrh_rddata_s2 = 8'hxx;


@@ -373,6 +378,7 @@ module Memory(
                                cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
                                if(cur_reg == 4'hF && insn[22]) begin
                                        next_outcpsr = spsr;
                                cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
                                if(cur_reg == 4'hF && insn[22]) begin
                                        next_outcpsr = spsr;

+                                       next_outcpsrup = 1;

                                end
 
                                offset = prev_offset + 6'h4;
                                end
 
                                offset = prev_offset + 6'h4;


@@ -445,8 +451,10 @@ module Memory(
                                        next_write_reg = 1'b1;
                                        next_write_num = insn[15:12];
                                        next_write_data = cp_read;
                                        next_write_reg = 1'b1;
                                        next_write_num = insn[15:12];
                                        next_write_data = cp_read;

-                               end else
+                               end else begin

                                        next_outcpsr = {cp_read[31:28], cpsr[27:0]};
                                        next_outcpsr = {cp_read[31:28], cpsr[27:0]};

+                                       next_outcpsrup = 1;
+                               end

                        end
                        if (cp_busy) begin
                                outstall = 1;
                        end
                        if (cp_busy) begin
                                outstall = 1;

diff --git a/Writeback.v b/Writeback.v
index b0e69cf91cfec00c07165c5d1e05c918b9c91a33..d0d43041f19cea96de24a85a3ed6397dfa349cbf 100644 (file)
--- a/Writeback.v
+++ b/Writeback.v
@@ -9,6 +9,7 @@ module Writeback(
        
        input [31:0] cpsr,
        input [31:0] spsr,
        
        input [31:0] cpsr,
        input [31:0] spsr,

+       input cpsrup,

        
        output reg regfile_write,
        output reg [3:0] regfile_write_reg,
        
        output reg regfile_write,
        output reg [3:0] regfile_write_reg,


@@ -23,13 +24,13 @@ module Writeback(
        reg [31:0] last_outcpsr = 0, last_outspsr = 0;
        
        always @(*)
        reg [31:0] last_outcpsr = 0, last_outspsr = 0;
        
        always @(*)

-               if (inbubble)
+               if (inbubble || !cpsrup)

                        outcpsr = last_outcpsr;
                else
                        outcpsr = cpsr;
        
        always @(*)
                        outcpsr = last_outcpsr;
                else
                        outcpsr = cpsr;
        
        always @(*)

-               if (inbubble)
+               if (inbubble || !cpsrup)

                        outspsr = last_outspsr;
                else
                        outspsr = spsr;
                        outspsr = last_outspsr;
                else
                        outspsr = spsr;

diff --git a/system.v b/system.v
index 1635a34159471ec94291a13d3569e1e5eeecd4e8..17412039d77b1b7827a0e8a4adb27ea797ac17d1 100644 (file)
--- a/system.v
+++ b/system.v
@@ -60,6 +60,7 @@ module System(input clk);
        wire [31:0] execute_out_write_data;
        wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
        wire [31:0] execute_out_cpsr, execute_out_spsr;
        wire [31:0] execute_out_write_data;
        wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
        wire [31:0] execute_out_cpsr, execute_out_spsr;

+       wire execute_out_cpsrup;

        
        wire jmp_out_execute, jmp_out_writeback;
        wire [31:0] jmppc_out_execute, jmppc_out_writeback;
        
        wire jmp_out_execute, jmp_out_writeback;
        wire [31:0] jmppc_out_execute, jmppc_out_writeback;


@@ -70,6 +71,7 @@ module System(input clk);
        wire [3:0] memory_out_write_num;
        wire [31:0] memory_out_write_data;
        wire [31:0] memory_out_cpsr, memory_out_spsr;
        wire [3:0] memory_out_write_num;
        wire [31:0] memory_out_write_data;
        wire [31:0] memory_out_cpsr, memory_out_spsr;

+       wire memory_out_cpsrup;

        
        wire [31:0] writeback_out_cpsr, writeback_out_spsr;
 
        
        wire [31:0] writeback_out_cpsr, writeback_out_spsr;
 


@@ -177,7 +179,7 @@ module System(input clk);
                .jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
                .outpc(pc_out_execute), .outinsn(insn_out_execute),
                .outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
                .jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
                .outpc(pc_out_execute), .outinsn(insn_out_execute),
                .outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),

-               .outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr));
+               .outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr), .outcpsrup(execute_out_cpsrup));

        assign execute_out_backflush = jmp;
        
        assign cp_insn = insn_out_execute;
        assign execute_out_backflush = jmp;
        
        assign cp_insn = insn_out_execute;


@@ -189,14 +191,14 @@ module System(input clk);
                .st_read(regfile_read_3), .st_data(regfile_rdata_3),
                .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
                .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
                .st_read(regfile_read_3), .st_data(regfile_rdata_3),
                .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
                .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),

-               .spsr(execute_out_spsr), .cpsr(execute_out_cpsr),
+               .spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),

                .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
                .outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
                .outpc(pc_out_memory), .outinsn(insn_out_memory),
                .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
                .out_write_data(memory_out_write_data),
                .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
                .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
                .outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
                .outpc(pc_out_memory), .outinsn(insn_out_memory),
                .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
                .out_write_data(memory_out_write_data),
                .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),

-               .outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr) /* XXX data_size */);
+               .outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr), .outcpsrup(memory_out_cpsrup) /* XXX data_size */);

        
        Terminal terminal(      
                .clk(clk),
        
        Terminal terminal(      
                .clk(clk),


@@ -207,7 +209,7 @@ module System(input clk);
                .clk(clk),
                .inbubble(bubble_out_memory),
                .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
                .clk(clk),
                .inbubble(bubble_out_memory),
                .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),

-               .cpsr(memory_out_cpsr), .spsr(memory_out_spsr),
+               .cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),

                .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
                .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr), 
                .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
                .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
                .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr), 
                .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));