Memory.v

   1 `include "ARM_Constants.v"
   2
   3 module Memory(
   4         input clk,
   5         input Nrst,
   6
   7         input flush,
   8
   9         /* bus interface */
  10         output reg [31:0] busaddr,
  11         output reg rd_req,
  12         output reg wr_req,
  13         input rw_wait,
  14         output reg [31:0] wr_data,
  15         input [31:0] rd_data,
  16         output reg [2:0] data_size,
  17
  18         /* regfile interface */
  19         output reg [3:0] st_read,
  20         input [31:0] st_data,
  21
  22         /* Coprocessor interface */
  23         output reg cp_req,
  24         input cp_ack,
  25         input cp_busy,
  26         output reg cp_rnw,      /* 1 = read from CP, 0 = write to CP */
  27         input [31:0] cp_read,
  28         output reg [31:0] cp_write,
  29
  30         /* stage inputs */
  31         input inbubble,
  32         input [31:0] pc,
  33         input [31:0] insn,
  34         input [31:0] op0,
  35         input [31:0] op1,
  36         input [31:0] op2,
  37         input [31:0] spsr,
  38         input [31:0] cpsr,
  39         input write_reg,
  40         input [3:0] write_num,
  41         input [31:0] write_data,
  42
  43         /* outputs */
  44         output reg outstall,
  45         output reg outbubble,
  46         output reg [31:0] outpc,
  47         output reg [31:0] outinsn,
  48         output reg out_write_reg = 1'b0,
  49         output reg [3:0] out_write_num = 4'bxxxx,
  50         output reg [31:0] out_write_data = 32'hxxxxxxxx,
  51         output reg [31:0] outspsr = 32'hxxxxxxxx,
  52         output reg [31:0] outcpsr = 32'hxxxxxxxx
  53         );
  54
  55         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
  56         reg [31:0] prevaddr;
  57         reg [3:0] next_regsel, cur_reg, prev_reg;
  58         reg next_writeback;
  59
  60         reg next_outbubble;
  61         reg next_write_reg;
  62         reg [3:0] next_write_num;
  63         reg [31:0] next_write_data;
  64
  65         reg [2:0] lsr_state = 3'b001, next_lsr_state;
  66         reg [31:0] align_s1, align_s2, align_rddata;
  67
  68         reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
  69         reg [31:0] lsrh_rddata;
  70         reg [15:0] lsrh_rddata_s1;
  71         reg [7:0] lsrh_rddata_s2;
  72
  73         reg [15:0] regs, next_regs;
  74         reg [3:0] lsm_state = 4'b0001, next_lsm_state;
  75         reg [5:0] offset, prev_offset, offset_sel;
  76
  77         reg [31:0] swp_oldval, next_swp_oldval;
  78         reg [1:0] swp_state = 2'b01, next_swp_state;
  79
  80         always @(posedge clk)
  81         begin
  82                 outpc <= pc;
  83                 outinsn <= insn;
  84                 outbubble <= next_outbubble;
  85                 out_write_reg <= next_write_reg;
  86                 out_write_num <= next_write_num;
  87                 out_write_data <= next_write_data;
  88                 regs <= next_regs;
  89                 prev_reg <= cur_reg;
  90                 if (!rw_wait)
  91                         prev_offset <= offset;
  92                 prev_raddr <= raddr;
  93                 outcpsr <= next_outcpsr;
  94                 outspsr <= spsr;
  95                 swp_state <= next_swp_state;
  96                 lsm_state <= next_lsm_state;
  97                 lsr_state <= next_lsr_state;
  98                 lsrh_state <= next_lsrh_state;
  99                 prevaddr <= addr;
 100         end
 101
 102         reg delayedflush = 0;
 103         always @(posedge clk)
 104                 if (flush && outstall /* halp! I can't do it now, maybe later? */)
 105                         delayedflush <= 1;
 106                 else if (!outstall /* anything has been handled this time around */)
 107                         delayedflush <= 0;
 108
 109         always @(*)
 110         begin
 111                 addr = prevaddr;
 112                 raddr = 32'hxxxxxxxx;
 113                 rd_req = 1'b0;
 114                 wr_req = 1'b0;
 115                 wr_data = 32'hxxxxxxxx;
 116                 busaddr = 32'hxxxxxxxx;
 117                 data_size = 3'bxxx;
 118                 outstall = 1'b0;
 119                 next_write_reg = write_reg;
 120                 next_write_num = write_num;
 121                 next_write_data = write_data;
 122                 next_outbubble = inbubble;
 123                 next_regs = regs;
 124                 cp_req = 1'b0;
 125                 cp_rnw = 1'bx;
 126                 cp_write = 32'hxxxxxxxx;
 127                 offset = prev_offset;
 128                 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
 129                 lsrh_rddata = 32'hxxxxxxxx;
 130                 lsrh_rddata_s1 = 16'hxxxx;
 131                 lsrh_rddata_s2 = 8'hxx;
 132                 next_lsm_state = lsm_state;
 133                 next_lsr_state = lsr_state;
 134                 next_lsrh_state = lsrh_state;
 135                 next_swp_oldval = swp_oldval;
 136                 next_swp_state = swp_state;
 137                 cur_reg = prev_reg;
 138
 139                 /* XXX shit not given about endianness */
 140                 casez(insn)
 141                 `DECODE_ALU_SWP: if(!inbubble) begin
 142                         outstall = rw_wait;
 143                         next_outbubble = rw_wait;
 144                         busaddr = {op0[31:2], 2'b0};
 145                         data_size = insn[22] ? 3'b001 : 3'b100;
 146                         case(swp_state)
 147                         2'b01: begin
 148                                 rd_req = 1'b1;
 149                                 outstall = 1'b1;
 150                                 if(!rw_wait) begin
 151                                         next_swp_state = 2'b10;
 152                                         next_swp_oldval = rd_data;
 153                                 end
 154                                 $display("SWP: read stage");
 155                         end
 156                         2'b10: begin
 157                                 wr_req = 1'b1;
 158                                 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
 159                                 next_write_reg = 1'b1;
 160                                 next_write_num = insn[15:12];
 161                                 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
 162                                 if(!rw_wait)
 163                                         next_swp_state = 2'b01;
 164                                 $display("SWP: write stage");
 165                         end
 166                         default: begin end
 167                         endcase
 168                 end
 169                 `DECODE_ALU_MULT: begin end
 170                 `DECODE_ALU_HDATA_REG,
 171                 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
 172                         next_outbubble = rw_wait;
 173                         outstall = rw_wait;
 174                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
 175                         raddr = insn[24] ? op0 : addr; /* pre/post increment */
 176                         busaddr = raddr;
 177                         /* rotate to correct position */
 178                         case(insn[6:5])
 179                         2'b00: begin end /* swp */
 180                         2'b01: begin /* unsigned half */
 181                                 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
 182                                 data_size = 3'b010;
 183                                 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
 184                         end
 185                         2'b10: begin /* signed byte */
 186                                 wr_data = {4{op2[7:0]}};
 187                                 data_size = 3'b001;
 188                                 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
 189                                 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
 190                                 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
 191                         end
 192                         2'b11: begin /* signed half */
 193                                 wr_data = {2{op2[15:0]}};
 194                                 data_size = 3'b010;
 195                                 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
 196                         end
 197                         endcase
 198
 199                         case(lsrh_state)
 200                         3'b001: begin
 201                                 rd_req = insn[20];
 202                                 wr_req = ~insn[20];
 203                                 next_write_num = insn[15:12];
 204                                 next_write_data = lsrh_rddata;
 205                                 if(insn[20]) begin
 206                                         next_write_reg = 1'b1;
 207                                 end
 208                                 if(insn[21] | !insn[24]) begin
 209                                         outstall = 1'b1;
 210                                         if(!rw_wait)
 211                                                 next_lsrh_state = 3'b010;
 212                                 end
 213                                 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
 214                         end
 215                         3'b010: begin
 216                                 next_outbubble = 1'b0;
 217                                 next_write_reg = 1'b1;
 218                                 next_write_num = insn[19:16];
 219                                 next_write_data = addr;
 220                                 next_lsrh_state = 3'b100;
 221                         end
 222                         3'b100: begin
 223                                 outstall = 0;
 224                                 next_lsrh_state = 3'b001;
 225                         end
 226                         default: begin end
 227                         endcase
 228
 229                         if ((lsrh_state == 3'b001) && flush) begin      /* Reject it. */
 230                                 outstall = 1'b0;
 231                                 next_lsrh_state = 3'b001;
 232                         end
 233                 end
 234                 `DECODE_LDRSTR_UNDEFINED: begin end
 235                 `DECODE_LDRSTR: if(!inbubble) begin
 236                         next_outbubble = rw_wait;
 237                         outstall = rw_wait;
 238                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
 239                         raddr = insn[24] ? addr : op0; /* pre/post increment */
 240                         busaddr = raddr;
 241                         /* rotate to correct position */
 242                         align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
 243                         align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
 244                         /* select byte or word */
 245                         align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
 246                         wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
 247                         data_size = insn[22] ? 3'b001 : 3'b100;
 248                         case(lsr_state)
 249                         3'b001: begin
 250                                 rd_req = insn[20] /* L */;
 251                                 wr_req = ~insn[20] /* L */;
 252                                 next_write_reg = insn[20] /* L */;
 253                                 next_write_num = insn[15:12];
 254                                 if(insn[20] /* L */) begin
 255                                         next_write_data = align_rddata;
 256                                 end
 257                                 if(insn[21] /* W */ | !insn[24] /* P */) begin
 258                                         outstall = 1'b1;
 259                                         if(!rw_wait)
 260                                                 next_lsr_state = 3'b010;
 261                                 end
 262                                 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
 263                         end
 264                         3'b010: begin
 265                                 outstall = 1;
 266                                 next_outbubble = 0;
 267                                 next_write_reg = 1'b1;
 268                                 next_write_num = insn[19:16];
 269                                 next_write_data = addr;
 270                                 next_lsr_state = 3'b100;
 271                         end
 272                         3'b100: begin
 273                                 outstall = 0;
 274                                 next_lsr_state = 3'b001;
 275                         end
 276                         default: begin end
 277                         endcase
 278
 279                         if ((lsr_state == 3'b001) && flush) begin       /* Reject it. */
 280                                 outstall = 1'b0;
 281                                 next_lsr_state = 3'b001;
 282                         end
 283                 end
 284                 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
 285                 `DECODE_LDMSTM: if(!inbubble) begin
 286                         outstall = rw_wait;
 287                         next_outbubble = rw_wait;
 288                         data_size = 3'b100;
 289                         case(lsm_state)
 290                         4'b0001: begin
 291 //                              next_regs = insn[23] ? op1[15:0] : op1[0:15];
 292                                 /** verilator can suck my dick */
 293                                 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
 294                                 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
 295                                                                             op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
 296                                 offset = 6'b0;
 297                                 outstall = 1'b1;
 298                                 next_lsm_state = 4'b0010;
 299                         end
 300                         4'b0010: begin
 301                                 rd_req = insn[20];
 302                                 wr_req = ~insn[20];
 303                                 casez(regs)
 304                                 16'b???????????????1: begin
 305                                         cur_reg = 4'h0;
 306                                         next_regs = {regs[15:1], 1'b0};
 307                                 end
 308                                 16'b??????????????10: begin
 309                                         cur_reg = 4'h1;
 310                                         next_regs = {regs[15:2], 2'b0};
 311                                 end
 312                                 16'b?????????????100: begin
 313                                         cur_reg = 4'h2;
 314                                         next_regs = {regs[15:3], 3'b0};
 315                                 end
 316                                 16'b????????????1000: begin
 317                                         cur_reg = 4'h3;
 318                                         next_regs = {regs[15:4], 4'b0};
 319                                 end
 320                                 16'b???????????10000: begin
 321                                         cur_reg = 4'h4;
 322                                         next_regs = {regs[15:5], 5'b0};
 323                                 end
 324                                 16'b??????????100000: begin
 325                                         cur_reg = 4'h5;
 326                                         next_regs = {regs[15:6], 6'b0};
 327                                 end
 328                                 16'b?????????1000000: begin
 329                                         cur_reg = 4'h6;
 330                                         next_regs = {regs[15:7], 7'b0};
 331                                 end
 332                                 16'b????????10000000: begin
 333                                         cur_reg = 4'h7;
 334                                         next_regs = {regs[15:8], 8'b0};
 335                                 end
 336                                 16'b???????100000000: begin
 337                                         cur_reg = 4'h8;
 338                                         next_regs = {regs[15:9], 9'b0};
 339                                 end
 340                                 16'b??????1000000000: begin
 341                                         cur_reg = 4'h9;
 342                                         next_regs = {regs[15:10], 10'b0};
 343                                 end
 344                                 16'b?????10000000000: begin
 345                                         cur_reg = 4'hA;
 346                                         next_regs = {regs[15:11], 11'b0};
 347                                 end
 348                                 16'b????100000000000: begin
 349                                         cur_reg = 4'hB;
 350                                         next_regs = {regs[15:12], 12'b0};
 351                                 end
 352                                 16'b???1000000000000: begin
 353                                         cur_reg = 4'hC;
 354                                         next_regs = {regs[15:13], 13'b0};
 355                                 end
 356                                 16'b??10000000000000: begin
 357                                         cur_reg = 4'hD;
 358                                         next_regs = {regs[15:14], 14'b0};
 359                                 end
 360                                 16'b?100000000000000: begin
 361                                         cur_reg = 4'hE;
 362                                         next_regs = {regs[15], 15'b0};
 363                                 end
 364                                 16'b1000000000000000: begin
 365                                         cur_reg = 4'hF;
 366                                         next_regs = 16'b0;
 367                                 end
 368                                 default: begin
 369                                         cur_reg = 4'hx;
 370                                         next_regs = 16'b0;
 371                                 end
 372                                 endcase
 373                                 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
 374                                 if(cur_reg == 4'hF && insn[22]) begin
 375                                         next_outcpsr = spsr;
 376                                 end
 377
 378                                 offset = prev_offset + 6'h4;
 379                                 offset_sel = insn[24] ? offset : prev_offset;
 380                                 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
 381                                 if(insn[20]) begin
 382                                         next_write_reg = !rw_wait;
 383                                         next_write_num = cur_reg;
 384                                         next_write_data = rd_data;
 385                                 end
 386                                 if (rw_wait) begin
 387                                         next_regs = regs;
 388                                         cur_reg = prev_reg;     /* whoops, do this one again */
 389                                 end
 390
 391                                 st_read = cur_reg;
 392                                 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
 393                                 busaddr = raddr;
 394
 395                                 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
 396
 397                                 outstall = 1'b1;
 398
 399                                 if(next_regs == 16'b0) begin
 400                                         next_lsm_state = 4'b0100;
 401                                 end
 402                         end
 403                         4'b0100: begin
 404                                 outstall = 1;
 405                                 next_outbubble = 0;
 406                                 next_write_reg = insn[21] /* writeback */;
 407                                 next_write_num = insn[19:16];
 408                                 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
 409                                 next_lsm_state = 4'b1000;
 410                                 $display("LDMSTM: Stage 3: Writing back");
 411                         end
 412                         4'b1000: begin
 413                                 outstall = 0;
 414                                 next_lsm_state = 4'b0001;
 415                         end
 416                         default: $stop;
 417                         endcase
 418                         if ((lsm_state == 4'b0001) && flush) begin      /* Reject it. */
 419                                 outstall = 1'b0;
 420                                 next_lsm_state = 4'b0001;
 421                         end
 422                         $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
 423                 end
 424                 `DECODE_LDCSTC: if(!inbubble) begin
 425                         $display("WARNING: Unimplemented LDCSTC");
 426                 end
 427                 `DECODE_CDP: if(!inbubble) begin
 428                         cp_req = 1;
 429                         if (cp_busy) begin
 430                                 outstall = 1;
 431                                 next_outbubble = 1;
 432                         end
 433                         if (!cp_ack) begin
 434                                 /* XXX undefined instruction trap */
 435                                 $display("WARNING: Possible CDP undefined instruction");
 436                         end
 437                 end
 438                 `DECODE_MRCMCR: if(!inbubble) begin
 439                         cp_req = 1;
 440                         cp_rnw = insn[20] /* L */;
 441                         if (insn[20] == 0 /* store to coprocessor */)
 442                                 cp_write = op0;
 443                         else begin
 444                                 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
 445                                         next_write_reg = 1'b1;
 446                                         next_write_num = insn[15:12];
 447                                         next_write_data = cp_read;
 448                                 end else
 449                                         next_outcpsr = {cp_read[31:28], cpsr[27:0]};
 450                         end
 451                         if (cp_busy) begin
 452                                 outstall = 1;
 453                                 next_outbubble = 1;
 454                         end
 455                         if (!cp_ack) begin
 456                                 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
 457                         end
 458                         $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
 459                 end
 460                 default: begin end
 461                 endcase
 462
 463                 if ((flush || delayedflush) && !outstall)
 464                         next_outbubble = 1'b1;
 465         end
 466 endmodule