input clk,
/* ARM core interface */
- input [31:0] addr,
- input rd_req,
- input wr_req,
- output reg rw_wait,
- input [31:0] wr_data,
- output reg [31:0] rd_data,
+ input [31:0] dc__addr_3a,
+ input dc__rd_req_3a,
+ input dc__wr_req_3a,
+ output reg dc__rw_wait_3a,
+ input [31:0] dc__wr_data_3a,
+ output reg [31:0] dc__rd_data_3a,
/* bus interface */
output wire bus_req,
cache_tags[i[3:0]] = 0;
end
- wire [5:0] didx = addr[5:0];
+ wire [5:0] didx = dc__addr_3a[5:0];
wire [3:0] didx_word = didx[5:2];
- wire [3:0] idx = addr[9:6];
- wire [21:0] tag = addr[31:10];
+ wire [3:0] idx = dc__addr_3a[9:6];
+ wire [21:0] tag = dc__addr_3a[31:10];
reg [31:0] prev_addr = 32'hFFFFFFFF;
wire [31:0] curdata = cache_data[{idx,didx_word}];
always @(*) begin
- rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
- rd_data = curdata;
- if (!rw_wait && rd_req)
- $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data);
+ dc__rw_wait_3a = (dc__rd_req_3a && !cache_hit) || (dc__wr_req_3a && (!bus_ack || !bus_ready));
+ dc__rd_data_3a = curdata;
+ if (!dc__rw_wait_3a && dc__rd_req_3a)
+ $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", dc__addr_3a, dc__rd_data_3a);
end
reg [3:0] cache_fill_pos = 0;
- assign bus_req = (rd_req && !cache_hit) || wr_req;
+ assign bus_req = (dc__rd_req_3a && !cache_hit) || dc__wr_req_3a;
always @(*)
begin
bus_rd = 0;
bus_wr = 0;
bus_addr = 0;
bus_wdata = 0;
- if (rd_req && !cache_hit && bus_ack) begin
- bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
+ if (dc__rd_req_3a && !cache_hit && bus_ack) begin
+ bus_addr = {dc__addr_3a[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
bus_rd = 1;
- end else if (wr_req && bus_ack) begin
- $display("DCACHE: WRITE REQUEST: Addr %08x, data %08x", addr, wr_data);
- bus_addr = addr;
+ end else if (dc__wr_req_3a && bus_ack) begin
+ $display("DCACHE: WRITE REQUEST: Addr %08x, data %08x", dc__addr_3a, dc__wr_data_3a);
+ bus_addr = dc__addr_3a;
bus_wr = 1;
- bus_wdata = wr_data;
+ bus_wdata = dc__wr_data_3a;
end
end
always @(posedge clk) begin
- prev_addr <= {addr[31:6], 6'b0};
- if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
+ prev_addr <= {dc__addr_3a[31:6], 6'b0};
+ if (dc__rd_req_3a && (cache_fill_pos != 0) && ((prev_addr != {dc__addr_3a[31:6], 6'b0}) || cache_hit)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
cache_fill_pos <= 0;
- else if (rd_req && !cache_hit && bus_ready && bus_ack) begin /* Started the fill, and we have data. */
- $display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", addr, bus_addr, bus_rdata, bus_req, bus_ack);
+ else if (dc__rd_req_3a && !cache_hit && bus_ready && bus_ack) begin /* Started the fill, and we have data. */
+ $display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", dc__addr_3a, bus_addr, bus_rdata, bus_req, bus_ack);
cache_fill_pos <= cache_fill_pos + 1;
if (cache_fill_pos == 15) begin /* Done? */
cache_tags[idx] <= tag;
end
/* Split this out because XST is kind of silly about this sort of thing. */
- if ((rd_req && !cache_hit && bus_ready && bus_ack) || (wr_req && cache_hit))
- cache_data[wr_req ? {idx,addr[5:2]} : {idx,cache_fill_pos}] <= wr_req ? wr_data : bus_rdata;
+ if ((dc__rd_req_3a && !cache_hit && bus_ready && bus_ack) || (dc__wr_req_3a && cache_hit))
+ cache_data[dc__wr_req_3a ? {idx,dc__addr_3a[5:2]} : {idx,cache_fill_pos}] <= dc__wr_req_3a ? dc__wr_data_3a : bus_rdata;
end
endmodule
wire [31:0] cpsr_2a; // From decode of Decode.v
wire [31:0] cpsr_3a; // From execute of Execute.v
wire cpsrup_3a; // From execute of Execute.v
+ wire [31:0] dc__addr_3a; // From memory of Memory.v
wire [2:0] dc__data_size_3a; // From memory of Memory.v
+ wire [31:0] dc__rd_data_3a; // From dcache of DCache.v
+ wire dc__rd_req_3a; // From memory of Memory.v
+ wire dc__rw_wait_3a; // From dcache of DCache.v
+ wire [31:0] dc__wr_data_3a; // From memory of Memory.v
+ wire dc__wr_req_3a; // From memory of Memory.v
wire [31:0] ic__rd_addr_0a; // From fetch of Fetch.v
wire [31:0] ic__rd_data_1a; // From icache of ICache.v
wire ic__rd_req_0a; // From fetch of Fetch.v
.bus_wr(bus_wr_icache),
.bus_ready(bus_ready),
); */
- ICache icache(/*AUTOINST*/
+ ICache icache(
+ /*AUTOINST*/
// Outputs
.ic__rd_wait_0a (ic__rd_wait_0a),
.ic__rd_data_1a (ic__rd_data_1a[31:0]),
.bus_rdata (bus_rdata), // Templated
.bus_ready (bus_ready)); // Templated
- DCache dcache(
+ /* DCache AUTO_TEMPLATE (
.clk(clk),
- .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
- .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
- .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
- .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
- .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
- .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
+ .bus_req(bus_req_dcache),
+ .bus_ack(bus_ack_dcache),
+ .bus_addr(bus_addr_dcache),
+ .bus_rdata(bus_rdata),
+ .bus_wdata(bus_wdata_dcache),
+ .bus_rd(bus_rd_dcache),
+ .bus_wr(bus_wr_dcache),
+ .bus_ready(bus_ready),
+ );
+ */
+ DCache dcache(
+ /*AUTOINST*/
+ // Outputs
+ .dc__rw_wait_3a (dc__rw_wait_3a),
+ .dc__rd_data_3a (dc__rd_data_3a[31:0]),
+ .bus_req (bus_req_dcache), // Templated
+ .bus_addr (bus_addr_dcache), // Templated
+ .bus_wdata (bus_wdata_dcache), // Templated
+ .bus_rd (bus_rd_dcache), // Templated
+ .bus_wr (bus_wr_dcache), // Templated
+ // Inputs
+ .clk (clk), // Templated
+ .dc__addr_3a (dc__addr_3a[31:0]),
+ .dc__rd_req_3a (dc__rd_req_3a),
+ .dc__wr_req_3a (dc__wr_req_3a),
+ .dc__wr_data_3a (dc__wr_data_3a[31:0]),
+ .bus_ack (bus_ack_dcache), // Templated
+ .bus_rdata (bus_rdata), // Templated
+ .bus_ready (bus_ready)); // Templated
`ifdef verilator
BigBlockRAM
/* stall? */
/* Memory AUTO_TEMPLATE (
.flush(writeback_out_backflush),
- .dc__addr_3a(dcache_addr),
- .dc__rd_req_3a(dcache_rd_req),
- .dc__wr_req_3a(dcache_wr_req),
- .dc__rw_wait_3a(dcache_rw_wait),
- .dc__wr_data_3a(dcache_wr_data),
- .dc__rd_data_3a(dcache_rd_data),
.outstall(stall_cause_memory),
.outbubble(bubble_out_memory),
.outpc(pc_out_memory),
Memory memory(
/*AUTOINST*/
// Outputs
- .dc__addr_3a (dcache_addr), // Templated
- .dc__rd_req_3a (dcache_rd_req), // Templated
- .dc__wr_req_3a (dcache_wr_req), // Templated
- .dc__wr_data_3a (dcache_wr_data), // Templated
+ .dc__addr_3a (dc__addr_3a[31:0]),
+ .dc__rd_req_3a (dc__rd_req_3a),
+ .dc__wr_req_3a (dc__wr_req_3a),
+ .dc__wr_data_3a (dc__wr_data_3a[31:0]),
.dc__data_size_3a (dc__data_size_3a[2:0]),
.rf__read_3_3a (rf__read_3_3a[3:0]),
.cp_req (cp_req), // Templated
.clk (clk),
.Nrst (Nrst),
.flush (writeback_out_backflush), // Templated
- .dc__rw_wait_3a (dcache_rw_wait), // Templated
- .dc__rd_data_3a (dcache_rd_data), // Templated
+ .dc__rw_wait_3a (dc__rw_wait_3a),
+ .dc__rd_data_3a (dc__rd_data_3a[31:0]),
.rf__rdata_3_3a (rf__rdata_3_3a[31:0]),
.cp_ack (cp_ack), // Templated
.cp_busy (cp_busy), // Templated
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