system.v

   1 `define BUS_ICACHE 1
   2 `define BUS_DCACHE 0
   3
   4 module System(input clk, input rst
   5 `ifdef verilator
   6 `else
   7         , output wire [8:0] sys_odata,
   8         input [8:0] sys_idata,
   9         output wire sys_tookdata
  10 `endif
  11         );
  12
  13         wire [7:0] bus_req;
  14         wire [7:0] bus_ack;
  15         wire [31:0] bus_addr;
  16         wire [31:0] bus_rdata;
  17         wire [31:0] bus_wdata;
  18         wire bus_rd, bus_wr;
  19         wire bus_ready;
  20
  21         wire bus_req_icache;
  22         wire bus_req_dcache;
  23         assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
  24         wire bus_ack_icache = bus_ack[`BUS_ICACHE];
  25         wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
  26
  27         wire [31:0] bus_addr_icache;
  28         wire [31:0] bus_wdata_icache;
  29         wire bus_rd_icache;
  30         wire bus_wr_icache;
  31
  32         wire [31:0] bus_addr_dcache;
  33         wire [31:0] bus_wdata_dcache;
  34         wire bus_rd_dcache;
  35         wire bus_wr_dcache;
  36
  37         wire [31:0] bus_rdata_blockram;
  38         wire bus_ready_blockram;
  39
  40         assign bus_addr = bus_addr_icache | bus_addr_dcache;
  41         assign bus_rdata = bus_rdata_blockram;
  42         assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
  43         assign bus_rd = bus_rd_icache | bus_rd_dcache;
  44         assign bus_wr = bus_wr_icache | bus_wr_dcache;
  45         assign bus_ready = bus_ready_blockram;
  46
  47         wire [31:0] icache_rd_addr;
  48         wire icache_rd_req;
  49         wire icache_rd_wait;
  50         wire [31:0] icache_rd_data;
  51
  52         wire [31:0] dcache_addr;
  53         wire dcache_rd_req, dcache_wr_req;
  54         wire dcache_rw_wait;
  55         wire [31:0] dcache_wr_data, dcache_rd_data;
  56
  57         wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
  58         wire decode_out_carry;
  59
  60         wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
  61         wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
  62         wire regfile_write;
  63         wire [3:0] regfile_write_reg;
  64         wire [31:0] regfile_write_data;
  65
  66         wire execute_out_write_reg;
  67         wire [3:0] execute_out_write_num;
  68         wire [31:0] execute_out_write_data;
  69         wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
  70         wire [31:0] execute_out_cpsr, execute_out_spsr;
  71         wire execute_out_cpsrup;
  72
  73         wire jmp_out_execute, jmp_out_writeback;
  74         wire [31:0] jmppc_out_execute, jmppc_out_writeback;
  75         wire jmp = jmp_out_execute | jmp_out_writeback;
  76         wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
  77
  78         wire memory_out_write_reg;
  79         wire [3:0] memory_out_write_num;
  80         wire [31:0] memory_out_write_data;
  81         wire [31:0] memory_out_cpsr, memory_out_spsr;
  82         wire memory_out_cpsrup;
  83
  84         wire [31:0] writeback_out_cpsr, writeback_out_spsr;
  85
  86         wire cp_ack_terminal;
  87         wire cp_busy_terminal;
  88         wire [31:0] cp_read_terminal;
  89
  90         wire cp_req;
  91         wire [31:0] cp_insn;
  92         wire cp_ack = cp_ack_terminal;
  93         wire cp_busy = cp_busy_terminal;
  94         wire cp_rnw;
  95         wire [31:0] cp_read = cp_read_terminal;
  96         wire [31:0] cp_write;
  97
  98         wire stall_cause_issue;
  99         wire stall_cause_execute;
 100         wire stall_cause_memory;
 101         wire bubble_out_fetch;
 102         wire bubble_out_issue;
 103         wire bubble_out_execute;
 104         wire bubble_out_memory;
 105         wire [31:0] insn_out_fetch;
 106         wire [31:0] insn_out_issue;
 107         wire [31:0] insn_out_execute;
 108         wire [31:0] insn_out_memory;
 109         wire [31:0] pc_out_fetch;
 110         wire [31:0] pc_out_issue;
 111         wire [31:0] pc_out_execute;
 112         wire [31:0] pc_out_memory;
 113
 114         wire Nrst = ~rst;
 115
 116         /*AUTOWIRE*/
 117         // Beginning of automatic wires (for undeclared instantiated-module outputs)
 118         wire            bubble_1a;              // From fetch of Fetch.v
 119         wire            bubble_2a;              // From issue of Issue.v
 120         wire            bubble_3a;              // From execute of Execute.v
 121         wire            carry_2a;               // From decode of Decode.v
 122         wire [31:0]     cpsr_2a;                // From decode of Decode.v
 123         wire [31:0]     cpsr_3a;                // From execute of Execute.v
 124         wire            cpsrup_3a;              // From execute of Execute.v
 125         wire [31:0]     dc__addr_3a;            // From memory of Memory.v
 126         wire [2:0]      dc__data_size_3a;       // From memory of Memory.v
 127         wire [31:0]     dc__rd_data_3a;         // From dcache of DCache.v
 128         wire            dc__rd_req_3a;          // From memory of Memory.v
 129         wire            dc__rw_wait_3a;         // From dcache of DCache.v
 130         wire [31:0]     dc__wr_data_3a;         // From memory of Memory.v
 131         wire            dc__wr_req_3a;          // From memory of Memory.v
 132         wire [31:0]     ic__rd_addr_0a;         // From fetch of Fetch.v
 133         wire [31:0]     ic__rd_data_1a;         // From icache of ICache.v
 134         wire            ic__rd_req_0a;          // From fetch of Fetch.v
 135         wire            ic__rd_wait_0a;         // From icache of ICache.v
 136         wire [31:0]     insn_1a;                // From fetch of Fetch.v
 137         wire [31:0]     insn_2a;                // From issue of Issue.v
 138         wire [31:0]     insn_3a;                // From execute of Execute.v
 139         wire [31:0]     op0_2a;                 // From decode of Decode.v
 140         wire [31:0]     op0_3a;                 // From execute of Execute.v
 141         wire [31:0]     op1_2a;                 // From decode of Decode.v
 142         wire [31:0]     op1_3a;                 // From execute of Execute.v
 143         wire [31:0]     op2_2a;                 // From decode of Decode.v
 144         wire [31:0]     op2_3a;                 // From execute of Execute.v
 145         wire [31:0]     pc_1a;                  // From fetch of Fetch.v
 146         wire [31:0]     pc_2a;                  // From issue of Issue.v
 147         wire [31:0]     pc_3a;                  // From execute of Execute.v
 148         wire [31:0]     rf__rdata_0_1a;         // From regfile of RegFile.v
 149         wire [31:0]     rf__rdata_1_1a;         // From regfile of RegFile.v
 150         wire [31:0]     rf__rdata_2_1a;         // From regfile of RegFile.v
 151         wire [31:0]     rf__rdata_3_3a;         // From regfile of RegFile.v
 152         wire [3:0]      rf__read_0_1a;          // From decode of Decode.v
 153         wire [3:0]      rf__read_1_1a;          // From decode of Decode.v
 154         wire [3:0]      rf__read_2_1a;          // From decode of Decode.v
 155         wire [3:0]      rf__read_3_3a;          // From memory of Memory.v
 156         wire [31:0]     spsr_2a;                // From decode of Decode.v
 157         wire [31:0]     spsr_3a;                // From execute of Execute.v
 158         wire            stall_0a;               // From issue of Issue.v
 159         wire [31:0]     write_data_3a;          // From execute of Execute.v
 160         wire [3:0]      write_num_3a;           // From execute of Execute.v
 161         wire            write_reg_3a;           // From execute of Execute.v
 162         // End of automatics
 163
 164         wire execute_out_backflush;
 165         wire writeback_out_backflush;
 166
 167         BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 168
 169         /* XXX reset? */
 170         /* ICache AUTO_TEMPLATE (
 171                 .clk(clk),
 172                 .bus_req(bus_req_icache),
 173                 .bus_ack(bus_ack_icache),
 174                 .bus_addr(bus_addr_icache),
 175                 .bus_rdata(bus_rdata),
 176                 .bus_wdata(bus_wdata_icache),
 177                 .bus_rd(bus_rd_icache),
 178                 .bus_wr(bus_wr_icache),
 179                 .bus_ready(bus_ready),
 180                 ); */
 181         ICache icache(
 182                 /*AUTOINST*/
 183                       // Outputs
 184                       .ic__rd_wait_0a   (ic__rd_wait_0a),
 185                       .ic__rd_data_1a   (ic__rd_data_1a[31:0]),
 186                       .bus_req          (bus_req_icache),        // Templated
 187                       .bus_addr         (bus_addr_icache),       // Templated
 188                       .bus_wdata        (bus_wdata_icache),      // Templated
 189                       .bus_rd           (bus_rd_icache),         // Templated
 190                       .bus_wr           (bus_wr_icache),         // Templated
 191                       // Inputs
 192                       .clk              (clk),                   // Templated
 193                       .ic__rd_addr_0a   (ic__rd_addr_0a[31:0]),
 194                       .ic__rd_req_0a    (ic__rd_req_0a),
 195                       .bus_ack          (bus_ack_icache),        // Templated
 196                       .bus_rdata        (bus_rdata),             // Templated
 197                       .bus_ready        (bus_ready));            // Templated
 198
 199         /* DCache AUTO_TEMPLATE (
 200                 .clk(clk),
 201                 .bus_req(bus_req_dcache),
 202                 .bus_ack(bus_ack_dcache),
 203                 .bus_addr(bus_addr_dcache),
 204                 .bus_rdata(bus_rdata),
 205                 .bus_wdata(bus_wdata_dcache),
 206                 .bus_rd(bus_rd_dcache),
 207                 .bus_wr(bus_wr_dcache),
 208                 .bus_ready(bus_ready),
 209                 );
 210                 */
 211         DCache dcache(
 212                 /*AUTOINST*/
 213                       // Outputs
 214                       .dc__rw_wait_3a   (dc__rw_wait_3a),
 215                       .dc__rd_data_3a   (dc__rd_data_3a[31:0]),
 216                       .bus_req          (bus_req_dcache),        // Templated
 217                       .bus_addr         (bus_addr_dcache),       // Templated
 218                       .bus_wdata        (bus_wdata_dcache),      // Templated
 219                       .bus_rd           (bus_rd_dcache),         // Templated
 220                       .bus_wr           (bus_wr_dcache),         // Templated
 221                       // Inputs
 222                       .clk              (clk),                   // Templated
 223                       .dc__addr_3a      (dc__addr_3a[31:0]),
 224                       .dc__rd_req_3a    (dc__rd_req_3a),
 225                       .dc__wr_req_3a    (dc__wr_req_3a),
 226                       .dc__wr_data_3a   (dc__wr_data_3a[31:0]),
 227                       .bus_ack          (bus_ack_dcache),        // Templated
 228                       .bus_rdata        (bus_rdata),             // Templated
 229                       .bus_ready        (bus_ready));            // Templated
 230
 231 `ifdef verilator
 232         BigBlockRAM
 233 `else
 234         BlockRAM
 235 `endif
 236         blockram(
 237                 .clk(clk),
 238                 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
 239                 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
 240                 .bus_ready(bus_ready_blockram));
 241
 242         /* Fetch AUTO_TEMPLATE (
 243                 .jmp_0a(jmp),
 244                 .jmppc_0a(jmppc),
 245                 );
 246         */
 247         Fetch fetch(
 248                 /*AUTOINST*/
 249                     // Outputs
 250                     .ic__rd_addr_0a     (ic__rd_addr_0a[31:0]),
 251                     .ic__rd_req_0a      (ic__rd_req_0a),
 252                     .bubble_1a          (bubble_1a),
 253                     .insn_1a            (insn_1a[31:0]),
 254                     .pc_1a              (pc_1a[31:0]),
 255                     // Inputs
 256                     .clk                (clk),
 257                     .Nrst               (Nrst),
 258                     .ic__rd_wait_0a     (ic__rd_wait_0a),
 259                     .ic__rd_data_1a     (ic__rd_data_1a[31:0]),
 260                     .stall_0a           (stall_0a),
 261                     .jmp_0a             (jmp),                   // Templated
 262                     .jmppc_0a           (jmppc));                // Templated
 263
 264         /* Issue AUTO_TEMPLATE (
 265                 .stall_1a(stall_cause_execute),
 266                 .flush_1a(execute_out_backflush | writeback_out_backflush),
 267                 .cpsr_1a(writeback_out_cpsr),
 268                 );
 269         */
 270         Issue issue(
 271                 /*AUTOINST*/
 272                     // Outputs
 273                     .stall_0a           (stall_0a),
 274                     .bubble_2a          (bubble_2a),
 275                     .pc_2a              (pc_2a[31:0]),
 276                     .insn_2a            (insn_2a[31:0]),
 277                     // Inputs
 278                     .clk                (clk),
 279                     .Nrst               (Nrst),
 280                     .stall_1a           (stall_cause_execute),   // Templated
 281                     .flush_1a           (execute_out_backflush | writeback_out_backflush), // Templated
 282                     .bubble_1a          (bubble_1a),
 283                     .insn_1a            (insn_1a[31:0]),
 284                     .pc_1a              (pc_1a[31:0]),
 285                     .cpsr_1a            (writeback_out_cpsr));   // Templated
 286
 287         /* RegFile AUTO_TEMPLATE (
 288                 .spsr(regfile_spsr),
 289                 .write(regfile_write),
 290                 .write_reg(regfile_write_reg),
 291                 .write_data(regfile_write_data),
 292                 );
 293         */
 294         wire [3:0] rf__read_3_4a;
 295         RegFile regfile(
 296                 /*AUTOINST*/
 297                         // Outputs
 298                         .rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
 299                         .rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
 300                         .rf__rdata_2_1a (rf__rdata_2_1a[31:0]),
 301                         .rf__rdata_3_3a (rf__rdata_3_3a[31:0]),
 302                         .spsr           (regfile_spsr),          // Templated
 303                         // Inputs
 304                         .clk            (clk),
 305                         .Nrst           (Nrst),
 306                         .rf__read_0_1a  (rf__read_0_1a[3:0]),
 307                         .rf__read_1_1a  (rf__read_1_1a[3:0]),
 308                         .rf__read_2_1a  (rf__read_2_1a[3:0]),
 309                         .rf__read_3_3a  (rf__read_3_3a[3:0]),
 310                         .write          (regfile_write),         // Templated
 311                         .write_reg      (regfile_write_reg),     // Templated
 312                         .write_data     (regfile_write_data));   // Templated
 313
 314         /* Decode AUTO_TEMPLATE (
 315                 .stall(stall_cause_execute),
 316                 .cpsr_1a(writeback_out_cpsr),
 317                 .spsr_1a(writeback_out_spsr),
 318                 );
 319         */
 320         Decode decode(
 321                 /*AUTOINST*/
 322                       // Outputs
 323                       .op0_2a           (op0_2a[31:0]),
 324                       .op1_2a           (op1_2a[31:0]),
 325                       .op2_2a           (op2_2a[31:0]),
 326                       .carry_2a         (carry_2a),
 327                       .cpsr_2a          (cpsr_2a[31:0]),
 328                       .spsr_2a          (spsr_2a[31:0]),
 329                       .rf__read_0_1a    (rf__read_0_1a[3:0]),
 330                       .rf__read_1_1a    (rf__read_1_1a[3:0]),
 331                       .rf__read_2_1a    (rf__read_2_1a[3:0]),
 332                       // Inputs
 333                       .clk              (clk),
 334                       .stall            (stall_cause_execute),   // Templated
 335                       .insn_1a          (insn_1a[31:0]),
 336                       .pc_1a            (pc_1a[31:0]),
 337                       .cpsr_1a          (writeback_out_cpsr),    // Templated
 338                       .spsr_1a          (writeback_out_spsr),    // Templated
 339                       .rf__rdata_0_1a   (rf__rdata_0_1a[31:0]),
 340                       .rf__rdata_1_1a   (rf__rdata_1_1a[31:0]),
 341                       .rf__rdata_2_1a   (rf__rdata_2_1a[31:0]));
 342
 343         /* Execute AUTO_TEMPLATE (
 344                 .stall_2a(stall_cause_memory),
 345                 .flush_2a(writeback_out_backflush),
 346                 .outstall_2a(stall_cause_execute),
 347                 .jmp_2a(jmp_out_execute),
 348                 .jmppc_2a(jmppc_out_execute),
 349                 );
 350         */
 351         Execute execute(
 352                 /*AUTOINST*/
 353                         // Outputs
 354                         .outstall_2a    (stall_cause_execute),   // Templated
 355                         .bubble_3a      (bubble_3a),
 356                         .cpsr_3a        (cpsr_3a[31:0]),
 357                         .spsr_3a        (spsr_3a[31:0]),
 358                         .cpsrup_3a      (cpsrup_3a),
 359                         .write_reg_3a   (write_reg_3a),
 360                         .write_num_3a   (write_num_3a[3:0]),
 361                         .write_data_3a  (write_data_3a[31:0]),
 362                         .jmppc_2a       (jmppc_out_execute),     // Templated
 363                         .jmp_2a         (jmp_out_execute),       // Templated
 364                         .pc_3a          (pc_3a[31:0]),
 365                         .insn_3a        (insn_3a[31:0]),
 366                         .op0_3a         (op0_3a[31:0]),
 367                         .op1_3a         (op1_3a[31:0]),
 368                         .op2_3a         (op2_3a[31:0]),
 369                         // Inputs
 370                         .clk            (clk),
 371                         .Nrst           (Nrst),
 372                         .stall_2a       (stall_cause_memory),    // Templated
 373                         .flush_2a       (writeback_out_backflush), // Templated
 374                         .bubble_2a      (bubble_2a),
 375                         .pc_2a          (pc_2a[31:0]),
 376                         .insn_2a        (insn_2a[31:0]),
 377                         .cpsr_2a        (cpsr_2a[31:0]),
 378                         .spsr_2a        (spsr_2a[31:0]),
 379                         .op0_2a         (op0_2a[31:0]),
 380                         .op1_2a         (op1_2a[31:0]),
 381                         .op2_2a         (op2_2a[31:0]),
 382                         .carry_2a       (carry_2a));
 383         assign execute_out_backflush = jmp;
 384
 385         assign cp_insn = insn_out_execute;
 386         /* stall? */
 387         /* Memory AUTO_TEMPLATE (
 388                 .flush(writeback_out_backflush),
 389                 .outstall(stall_cause_memory),
 390                 .outbubble(bubble_out_memory),
 391                 .outpc(pc_out_memory),
 392                 .outinsn(insn_out_memory),
 393                 .out_write_reg(memory_out_write_reg),
 394                 .out_write_num(memory_out_write_num),
 395                 .out_write_data(memory_out_write_data),
 396                 .cp_req(cp_req),
 397                 .cp_ack(cp_ack),
 398                 .cp_busy(cp_busy),
 399                 .cp_rnw(cp_rnw),
 400                 .cp_read(cp_read),
 401                 .cp_write(cp_write),
 402                 .outcpsr(memory_out_cpsr),
 403                 .outspsr(memory_out_spsr),
 404                 .outcpsrup(memory_out_cpsrup),
 405                 );
 406                 */
 407         Memory memory(
 408                 /*AUTOINST*/
 409                       // Outputs
 410                       .dc__addr_3a      (dc__addr_3a[31:0]),
 411                       .dc__rd_req_3a    (dc__rd_req_3a),
 412                       .dc__wr_req_3a    (dc__wr_req_3a),
 413                       .dc__wr_data_3a   (dc__wr_data_3a[31:0]),
 414                       .dc__data_size_3a (dc__data_size_3a[2:0]),
 415                       .rf__read_3_3a    (rf__read_3_3a[3:0]),
 416                       .cp_req           (cp_req),                // Templated
 417                       .cp_rnw           (cp_rnw),                // Templated
 418                       .cp_write         (cp_write),              // Templated
 419                       .outstall         (stall_cause_memory),    // Templated
 420                       .outbubble        (bubble_out_memory),     // Templated
 421                       .outpc            (pc_out_memory),         // Templated
 422                       .outinsn          (insn_out_memory),       // Templated
 423                       .out_write_reg    (memory_out_write_reg),  // Templated
 424                       .out_write_num    (memory_out_write_num),  // Templated
 425                       .out_write_data   (memory_out_write_data), // Templated
 426                       .outspsr          (memory_out_spsr),       // Templated
 427                       .outcpsr          (memory_out_cpsr),       // Templated
 428                       .outcpsrup        (memory_out_cpsrup),     // Templated
 429                       // Inputs
 430                       .clk              (clk),
 431                       .Nrst             (Nrst),
 432                       .flush            (writeback_out_backflush), // Templated
 433                       .dc__rw_wait_3a   (dc__rw_wait_3a),
 434                       .dc__rd_data_3a   (dc__rd_data_3a[31:0]),
 435                       .rf__rdata_3_3a   (rf__rdata_3_3a[31:0]),
 436                       .cp_ack           (cp_ack),                // Templated
 437                       .cp_busy          (cp_busy),               // Templated
 438                       .cp_read          (cp_read),               // Templated
 439                       .bubble_3a        (bubble_3a),
 440                       .pc_3a            (pc_3a[31:0]),
 441                       .insn_3a          (insn_3a[31:0]),
 442                       .op0_3a           (op0_3a[31:0]),
 443                       .op1_3a           (op1_3a[31:0]),
 444                       .op2_3a           (op2_3a[31:0]),
 445                       .spsr_3a          (spsr_3a[31:0]),
 446                       .cpsr_3a          (cpsr_3a[31:0]),
 447                       .cpsrup_3a        (cpsrup_3a),
 448                       .write_reg_3a     (write_reg_3a),
 449                       .write_num_3a     (write_num_3a[3:0]),
 450                       .write_data_3a    (write_data_3a[31:0]));
 451
 452         Terminal terminal(
 453                 .clk(clk),
 454                 .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
 455                 .cp_read(cp_read_terminal), .cp_write(cp_write)
 456 `ifdef verilator
 457 `else
 458                 , .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
 459 `endif
 460                 );
 461
 462         Writeback writeback(
 463                 .clk(clk),
 464                 .inbubble(bubble_out_memory),
 465                 .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
 466                 .cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
 467                 .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
 468                 .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr),
 469                 .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
 470         assign writeback_out_backflush = jmp_out_writeback;
 471
 472         reg [31:0] clockno = 0;
 473         always @(posedge clk)
 474         begin
 475                 clockno <= clockno + 1;
 476                 $display("------------------------------------------------------------------------------");
 477                 $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
 478                 $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_0a, bubble_2a, insn_2a, pc_2a);
 479                 $display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, op0_2a, op1_2a, op2_2a, carry_2a);
 480                 $display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
 481                 $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
 482                 $display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
 483         end
 484 endmodule