output reg [31:0] out_write_data = 32'hxxxxxxxx
);
- reg [31:0] addr, raddr;
- reg next_notdone, next_inc_next;
+ reg [31:0] addr, raddr, next_regdata;
+ reg [3:0] next_regsel, cur_reg, prev_reg;
+ reg next_writeback, next_notdone, next_inc_next;
reg [31:0] align_s1, align_s2, align_rddata;
+ wire next_outbubble;
wire next_write_reg;
wire [3:0] next_write_num;
wire [31:0] next_write_data;
next_write_num = write_num;
next_write_data = write_data;
next_inc_next = 1'b0;
+ next_outbubble = inbubble;
outstall = 1'b0;
-
+ next_regs = 16'b0;
+ next_started = started;
+
casez(insn)
`DECODE_LDRSTR_UNDEFINED: begin end
`DECODE_LDRSTR: begin