Memory.v

   1 `include "ARM_Constants.v"
   2
   3 module Memory(
   4         input clk,
   5         input Nrst,
   6
   7         /* bus interface */
   8         output reg [31:0] busaddr,
   9         output reg rd_req,
  10         output reg wr_req,
  11         input rw_wait,
  12         output reg [31:0] wr_data,
  13         input [31:0] rd_data,
  14
  15         /* regfile interface */
  16         output reg [3:0] st_read,
  17         input [31:0] st_data,
  18
  19         /* stage inputs */
  20         input inbubble,
  21         input [31:0] pc,
  22         input [31:0] insn,
  23         input [31:0] op0,
  24         input [31:0] op1,
  25         input [31:0] op2,
  26         input write_reg,
  27         input [3:0] write_num,
  28         input [31:0] write_data,
  29
  30         /* outputs */
  31         output reg outstall,
  32         output reg outbubble,
  33         output reg [31:0] outpc,
  34         output reg [31:0] outinsn,
  35         output reg out_write_reg = 1'b0,
  36         output reg [3:0] out_write_num = 4'bxxxx,
  37         output reg [31:0] out_write_data = 32'hxxxxxxxx
  38         );
  39
  40         reg [31:0] addr, raddr, next_regdata;
  41         reg [3:0] next_regsel, cur_reg, prev_reg;
  42         reg next_writeback, next_notdone, next_inc_next;
  43         reg [31:0] align_s1, align_s2, align_rddata;
  44
  45         wire next_write_reg;
  46         wire [3:0] next_write_num;
  47         wire [31:0] next_write_data;
  48
  49         reg [15:0] regs, next_regs;
  50         reg started = 1'b0, next_started;
  51
  52         reg notdone = 1'b0;
  53         reg inc_next = 1'b0;
  54
  55         always @(posedge clk)
  56         begin
  57                 outpc <= pc;
  58                 outinsn <= insn;
  59                 outbubble <= rw_wait;
  60                 out_write_reg <= next_writeback;
  61                 out_write_num <= next_regsel;
  62                 out_write_data <= next_regdata;
  63                 notdone <= next_notdone;
  64                 inc_next <= next_inc_next;
  65                 regs <= next_regs;
  66                 prev_reg <= cur_reg;
  67                 started <= next_started;
  68         end
  69
  70         always @(*)
  71         begin
  72                 addr = 32'hxxxxxxxx;
  73                 raddr = 32'hxxxxxxxx;
  74                 rd_req = 1'b0;
  75                 wr_req = 1'b0;
  76                 wr_data = 32'hxxxxxxxx;
  77                 busaddr = 32'hxxxxxxxx;
  78                 outstall = 1'b0;
  79                 next_notdone = 1'b0;
  80                 next_write_reg = write_reg;
  81                 next_write_num = write_num;
  82                 next_write_data = write_data;
  83                 next_inc_next = 1'b0;
  84                 outstall = 1'b0;
  85                 next_regs = 16'b0;
  86                 next_started = started;
  87
  88                 casez(insn)
  89                 `DECODE_LDRSTR_UNDEFINED: begin end
  90                 `DECODE_LDRSTR: begin
  91                         if (!inbubble) begin
  92                                 outstall = rw_wait | notdone;
  93
  94                                 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
  95                                 raddr = insn[24] ? op0 : addr; /* pre/post increment */
  96                                 busaddr = {raddr[31:2], 2'b0};
  97                                 rd_req = insn[20];
  98                                 wr_req = ~insn[20];
  99
 100                                 /* rotate to correct position */
 101                                 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
 102                                 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
 103                                 /* select byte or word */
 104                                 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
 105
 106                                 if(!insn[20]) begin
 107                                         wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
 108                                 end
 109                                 else if(!inc_next) begin
 110                                         next_write_reg = 1'b1;
 111                                         next_write_num = insn[15:12];
 112                                         next_write_data = align_rddata;
 113                                         next_inc_next = 1'b1;
 114                                 end
 115                                 else if(insn[21]) begin
 116                                         next_write_reg = 1'b1;
 117                                         next_write_num = insn[19:16];
 118                                         next_write_data = addr;
 119                                 end
 120                                 next_notdone = rw_wait & insn[20] & insn[21];
 121                         end
 122                 end
 123                 `DECODE_LDMSTM: begin
 124                         rd_req = insn[20];
 125                         wr_req = ~insn[20];
 126                         if(!started) begin
 127                                 next_regs = op1[15:0];
 128                                 next_started = 1'b1;
 129                         end
 130                         else if(inc_next) begin
 131                                 if(insn[21]) begin
 132                                         next_write_reg = 1'b1;
 133                                         next_write_num = insn[19:16];
 134                                         next_write_data = op0;
 135                                 end
 136                                 next_started = 1'b0;
 137                         end
 138                         else if(rw_wait) begin
 139                                 next_regs = regs;
 140                                 cur_reg = prev_reg;
 141                         end
 142                         else begin
 143                                 casez(regs)
 144                                 16'b???????????????1: begin
 145                                         cur_reg = 4'h0;
 146                                         next_regs = regs & 16'b1111111111111110;
 147                                 end
 148                                 16'b??????????????10: begin
 149                                         cur_reg = 4'h1;
 150                                         next_regs = regs & 16'b1111111111111100;
 151                                 end
 152                                 16'b?????????????100: begin
 153                                         cur_reg = 4'h2;
 154                                         next_regs = regs & 16'b1111111111111000;
 155                                 end
 156                                 16'b????????????1000: begin
 157                                         cur_reg = 4'h3;
 158                                         next_regs = regs & 16'b1111111111110000;
 159                                 end
 160                                 16'b???????????10000: begin
 161                                         cur_reg = 4'h4;
 162                                         next_regs = regs & 16'b1111111111100000;
 163                                 end
 164                                 16'b??????????100000: begin
 165                                         cur_reg = 4'h5;
 166                                         next_regs = regs & 16'b1111111111000000;
 167                                 end
 168                                 16'b?????????1000000: begin
 169                                         cur_reg = 4'h6;
 170                                         next_regs = regs & 16'b1111111110000000;
 171                                 end
 172                                 16'b????????10000000: begin
 173                                         cur_reg = 4'h7;
 174                                         next_regs = regs & 16'b1111111100000000;
 175                                 end
 176                                 16'b???????100000000: begin
 177                                         cur_reg = 4'h8;
 178                                         next_regs = regs & 16'b1111111000000000;
 179                                 end
 180                                 16'b??????1000000000: begin
 181                                         cur_reg = 4'h9;
 182                                         next_regs = regs & 16'b1111110000000000;
 183                                 end
 184                                 16'b?????10000000000: begin
 185                                         cur_reg = 4'hA;
 186                                         next_regs = regs & 16'b1111100000000000;
 187                                 end
 188                                 16'b????100000000000: begin
 189                                         cur_reg = 4'hB;
 190                                         next_regs = regs & 16'b1111000000000000;
 191                                 end
 192                                 16'b???1000000000000: begin
 193                                         cur_reg = 4'hC;
 194                                         next_regs = regs & 16'b1110000000000000;
 195                                 end
 196                                 16'b??10000000000000: begin
 197                                         cur_reg = 4'hD;
 198                                         next_regs = regs & 16'b1100000000000000;
 199                                 end
 200                                 16'b?100000000000000: begin
 201                                         cur_reg = 4'hE;
 202                                         next_regs = regs & 16'b1000000000000000;
 203                                 end
 204                                 16'b1000000000000000: begin
 205                                         cur_reg = 4'hF;
 206                                         next_regs = 16'b0;
 207                                 end
 208                                 default: begin
 209                                         cur_reg = 4'hx;
 210                                         next_regs = 16'b0;
 211                                 end
 212                                 endcase
 213                                 next_inc_next = next_regs == 16'b0;
 214                                 next_notdone = ~next_inc_next | (rw_wait & insn[20] & insn[21]);
 215                         end
 216                 end
 217                 default: begin end
 218                 endcase
 219         end
 220 endmodule