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Memory: Clean up some sadness with wr_data where no data would ever get wr'ed on...
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Mon, 9 Feb 2009 08:35:58 +0000 (03:35 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Mon, 9 Feb 2009 08:35:58 +0000 (03:35 -0500)

No differences found
FireARM pipelined ARM-like CPU implementation in Verilog
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