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Memory: Clean up some sadness with wr_data where no data would ever get wr'ed on...
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Mon, 9 Feb 2009 08:35:58 +0000 (03:35 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Mon, 9 Feb 2009 08:35:58 +0000 (03:35 -0500)
commite92804b313459de4a6fc444975a0537a3fba17ad
treed0d67be6b7d34de0cbec6f1cac84278dc70c6494tree | snapshot
parent8e30fdaf6744e2006ade689e6f7b89ee536449d0commit | diff
Memory: Clean up some sadness with wr_data where no data would ever get wr'ed on STM.
Memory.v diff | blob | blame | history
FireARM pipelined ARM-like CPU implementation in Verilog
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