module Decode(
input clk,
+ input stall,
input [31:0] insn,
input [31:0] inpc,
input [31:0] incpsr,
always @ (posedge clk) begin
- op0 <= op0_out; /* Rn - always */
- op1 <= op1_out; /* 'operand 2' - Rm */
- op2 <= op2_out; /* thirdedge - Rs */
- carry <= carry_out;
- outcpsr <= incpsr;
- outspsr <= inspsr;
+ if (!stall)
+ begin
+ op0 <= op0_out; /* Rn - always */
+ op1 <= op1_out; /* 'operand 2' - Rm */
+ op2 <= op2_out; /* thirdedge - Rs */
+ carry <= carry_out;
+ outcpsr <= incpsr;
+ outspsr <= inspsr;
+ end
end
endmodule
Decode decode(
.clk(clk),
+ .stall(stall_cause_execute),
.insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(writeback_out_cpsr), .inspsr(writeback_out_spsr),
.op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
.carry(decode_out_carry), .outcpsr(decode_out_cpsr), .outspsr(decode_out_spsr),