Merge nyus:/storage/git/firearm

Conflicts:

	Memory.v

diff --combined Decode.v
index b54104601f4dd8560b1c51bc37dbc683bf9a6e37,495942bee6d7282fb7ed9afa57348f067ef9d641..9bfb03ddf9e63c6b3c21c6a4b7bbf735faf67136
--- 1/Decode.v
--- 2/Decode.v
+++ b/Decode.v
@@@ -10,7 -10,6 +10,7 @@@ module Decode
        output reg [31:0] op1,
        output reg [31:0] op2,
        output reg carry,
 +      output reg [31:0] outcpsr,
        output reg [31:0] outspsr,
  
        output reg [3:0] read_0,
@@@ -139,16 -138,20 +139,20 @@@
                begin
                        read_0 = insn[19:16];
                        read_1 = insn[3:0];
-                       
+                       read_2 = insn[15:12];
+ 
                        op0_out = regs0;
                        op1_out = regs1;
+                       op2_out = regs2;
                end
                `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
                begin
                        read_0 = insn[19:16];
+                       read_1 = insn[15:12];
                        
                        op0_out = regs0;
                        op1_out = {24'b0, insn[11:8], insn[3:0]};
+                       op2_out = regs1;
                end
                `DECODE_ALU:            /* ALU */
                begin
@@@ -226,7 -229,6 +230,7 @@@
                op1 <= op1_out; /* 'operand 2' - Rm */
                op2 <= op2_out;   /* thirdedge - Rs */
                carry <= carry_out;
 +              outcpsr <= incpsr;
                outspsr <= inspsr;
        end
  

diff --combined Memory.v
index eb0f69f2ea8b7b21d58361ef5ad98c9a1fb3b10c,bfec0c068fed18f47eaf4c2fbb92f801d214ff17..eb4006f5884d3c71ccd7a5e20959a4238a2d4622
--- 1/Memory.v
--- 2/Memory.v
+++ b/Memory.v
@@@ -4,8 -4,6 +4,8 @@@ module Memory
        input clk,
        input Nrst,
  
 +      input flush,
 +
        /* bus interface */
        output reg [31:0] busaddr,
        output reg rd_req,
@@@ -13,6 -11,7 +13,7 @@@
        input rw_wait,
        output reg [31:0] wr_data,
        input [31:0] rd_data,
+       output reg [2:0] data_size,
  
        /* regfile interface */
        output reg [3:0] st_read,
@@@ -47,14 -46,14 +48,14 @@@
        output reg out_write_reg = 1'b0,
        output reg [3:0] out_write_num = 4'bxxxx,
        output reg [31:0] out_write_data = 32'hxxxxxxxx,
 -      output reg [31:0] out_spsr = 32'hxxxxxxxx,
 -      output reg [31:0] out_cpsr = 32'hxxxxxxxx
 +      output reg [31:0] outspsr = 32'hxxxxxxxx,
 +      output reg [31:0] outcpsr = 32'hxxxxxxxx
        );
  
        reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
+       reg [31:0] prevaddr;
        reg [3:0] next_regsel, cur_reg, prev_reg;
        reg next_writeback;
-       reg [31:0] align_s1, align_s2, align_rddata;
  
        wire next_outbubble;    
        wire next_write_reg;
@@@ -62,6 -61,12 +63,12 @@@
        wire [31:0] next_write_data;
  
        reg [1:0] lsr_state = 2'b01, next_lsr_state;
+       reg [31:0] align_s1, align_s2, align_rddata;
+ 
+       reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
+       reg [31:0] lsrh_rddata;
+       reg [15:0] lsrh_rddata_s1;
+       reg [7:0] lsrh_rddata_s2;
  
        reg [15:0] regs, next_regs;
        reg [2:0] lsm_state = 3'b001, next_lsm_state;
@@@ -82,46 -87,52 +89,54 @@@
                prev_reg <= cur_reg;
                prev_offset <= offset;
                prev_raddr <= raddr;
 -              out_cpsr <= next_outcpsr;
 -              out_spsr <= spsr;
 +              outcpsr <= next_outcpsr;
 +              outspsr <= spsr;
                swp_state <= next_swp_state;
+               lsm_state <= next_lsm_state;
+               lsr_state <= next_lsr_state;
+               lsrh_state <= next_lsrh_state;
+               prevaddr <= addr;
        end
  
        always @(*)
        begin
-               addr = 32'hxxxxxxxx;
+               addr = prevaddr;
                raddr = 32'hxxxxxxxx;
                rd_req = 1'b0;
                wr_req = 1'b0;
                wr_data = 32'hxxxxxxxx;
                busaddr = 32'hxxxxxxxx;
+               data_size = 3'bxxx;
                outstall = 1'b0;
                next_write_reg = write_reg;
                next_write_num = write_num;
                next_write_data = write_data;
                next_outbubble = inbubble;
-               outstall = 1'b0;
                next_regs = regs;
                cp_req = 1'b0;
                cp_rnw = 1'bx;
                cp_write = 32'hxxxxxxxx;
                offset = prev_offset;
 -              next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
 +              next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
+               lsrh_rddata = 32'hxxxxxxxx;
+               lsrh_rddata_s1 = 16'hxxxx;
+               lsrh_rddata_s2 = 8'hxx;
                next_lsm_state = lsm_state;
                next_lsr_state = lsr_state;
+               next_lsrh_state = lsrh_state;
                next_swp_oldval = swp_oldval;
                next_swp_state = swp_state;
                cur_reg = prev_reg;
  
                /* XXX shit not given about endianness */
-               /* TODO ldrh/strh */
 -              casez(insn)
 +              if (flush)
 +                      next_outbubble = 1'b1;
 +              else casez(insn)
                `DECODE_ALU_SWP: if(!inbubble) begin
                        outstall = rw_wait;
                        next_outbubble = rw_wait;
                        busaddr = {op0[31:2], 2'b0};
+                       data_size = insn[22] ? 3'b001 : 3'b100;
                        case(swp_state)
                        2'b01: begin
                                rd_req = 1'b1;
@@@ -133,41 -144,93 +148,93 @@@
                        end
                        2'b10: begin
                                wr_req = 1'b1;
-                               wr_data = op1;
+                               wr_data = insn[22] ? {4{op1[7:0]}} : op1;
                                next_write_reg = 1'b1;
                                next_write_num = insn[15:12];
-                               next_write_data = swp_oldval;
+                               next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
                                if(!rw_wait)
                                        next_swp_state = 2'b01;
                        end
                        default: begin end
                        endcase
                end
+               `DECODE_ALU_HDATA_REG,
+               `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
+                       next_outbubble = rw_wait;
+                       outstall = rw_wait;
+                       addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+                       raddr = insn[24] ? op0 : addr; /* pre/post increment */
+                       busaddr = raddr;
+                       /* rotate to correct position */
+                       case(insn[6:5])
+                       2'b00: begin end /* swp */
+                       2'b01: begin /* unsigned half */
+                               wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
+                               data_size = 3'b010;
+                               lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
+                       end
+                       2'b10: begin /* signed byte */
+                               wr_data = {4{op2[7:0]}};
+                               data_size = 3'b001;
+                               lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
+                               lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
+                               lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
+                       end
+                       2'b11: begin /* signed half */
+                               wr_data = {2{op2[15:0]}};
+                               data_size = 3'b010;
+                               lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
+                       end
+                       endcase
+ 
+                       case(lsrh_state)
+                       2'b01: begin
+                               rd_req = insn[20];
+                               wr_req = ~insn[20];
+                               next_write_num = insn[15:12];
+                               next_write_data = lsrh_rddata;
+                               if(insn[20]) begin
+                                       next_write_reg = 1'b1;
+                               end
+                               if(insn[21] | !insn[24]) begin
+                                       outstall = 1'b1;
+                                       if(!rw_wait)
+                                               next_lsrh_state = 2'b10;
+                               end
+                       end
+                       2'b10: begin
+                               next_write_reg = 1'b1;
+                               next_write_num = insn[19:16];
+                               next_write_data = addr;
+                               next_lsrh_state = 2'b10;
+                       end
+                       default: begin end
+                       endcase
+               end
                `DECODE_LDRSTR_UNDEFINED: begin end
                `DECODE_LDRSTR: if(!inbubble) begin
                        next_outbubble = rw_wait;
                        outstall = rw_wait;
                        addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
                        raddr = insn[24] ? op0 : addr; /* pre/post increment */
-                       busaddr = {raddr[31:2], 2'b0};
-                               /* rotate to correct position */
+                       busaddr = raddr;
+                       /* rotate to correct position */
                        align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
                        align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
                        /* select byte or word */
                        align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
-                       if(!insn[20]) begin
-                               wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
-                       end
+                       wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
+                       data_size = insn[22] ? 3'b001 : 3'b100;
                        case(lsr_state)
                        2'b01: begin
                                rd_req = insn[20];
                                wr_req = ~insn[20];
+                               next_write_reg = 1'b1;
+                               next_write_num = insn[15:12];
                                if(insn[20]) begin
-                                       next_write_reg = 1'b1;
-                                       next_write_num = insn[15:12];
                                        next_write_data = align_rddata;
                                end
-                                       if(insn[21]) begin
+                               if(insn[21] | !insn[24]) begin
                                        outstall = 1'b1;
                                        if(!rw_wait)
                                                next_lsr_state = 2'b10;
@@@ -186,6 -249,7 +253,7 @@@
                `DECODE_LDMSTM: if(!inbubble) begin
                        outstall = rw_wait;
                        next_outbubble = rw_wait;
+                       data_size = 3'b100;
                        case(lsm_state)
                        3'b001: begin
  //                            next_regs = insn[23] ? op1[15:0] : op1[0:15];
@@@ -292,7 -356,7 +360,7 @@@
  
                                st_read = cur_reg;
                                wr_data = st_data;
-                               busaddr = {raddr[31:2], 2'b0};
+                               busaddr = raddr;
  
                                outstall = 1'b1;