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Add special CPSR behavior for ARM MCR.
author
Joshua Wise
<joshua@rebirth.joshuawise.com>
Wed, 7 Jan 2009 09:58:34 +0000
(
04:58
-0500)
committer
Joshua Wise
<joshua@rebirth.joshuawise.com>
Wed, 7 Jan 2009 09:58:34 +0000
(
04:58
-0500)
Memory.v
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diff --git
a/Memory.v
b/Memory.v
index
c735ed9
..
ff9f397
100644
(file)
--- a/
Memory.v
+++ b/
Memory.v
@@
-325,9
+325,12
@@
module Memory(
if (insn[20] == 0 /* store to coprocessor */)
cp_write = op0;
else begin
if (insn[20] == 0 /* store to coprocessor */)
cp_write = op0;
else begin
- next_write_reg = 1'b1;
- next_write_num = insn[15:12];
- next_write_data = cp_read;
+ if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
+ next_write_reg = 1'b1;
+ next_write_num = insn[15:12];
+ next_write_data = cp_read;
+ end else
+ next_outcpsr = {cp_read[31:28], cpsr[27:0]};
end
if (cp_busy) begin
outstall = 1;
end
if (cp_busy) begin
outstall = 1;
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