From d1d0eb8e5614d620d5a62713ed11c0e34470f64e Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Wed, 7 Jan 2009 04:58:34 -0500 Subject: [PATCH] Add special CPSR behavior for ARM MCR. --- Memory.v | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Memory.v b/Memory.v index c735ed9..ff9f397 100644 --- a/Memory.v +++ b/Memory.v @@ -325,9 +325,12 @@ module Memory( if (insn[20] == 0 /* store to coprocessor */) cp_write = op0; else begin - next_write_reg = 1'b1; - next_write_num = insn[15:12]; - next_write_data = cp_read; + if (insn[15:12] != 4'hF /* Fuck you ARM */) begin + next_write_reg = 1'b1; + next_write_num = insn[15:12]; + next_write_data = cp_read; + end else + next_outcpsr = {cp_read[31:28], cpsr[27:0]}; end if (cp_busy) begin outstall = 1; -- 2.39.2