ICache: Change cache_data to block RAM (yay!).

diff --git a/Fetch.v b/Fetch.v
index fc4d899baae1d9baae0606503d71d5aaffed425f..bc2175cc90994ccb015ed8b9d37da9c0067023a4 100644 (file)
--- a/Fetch.v
+++ b/Fetch.v
@@ -47,7 +47,6 @@ module Fetch(
        assign ic__rd_addr_0a = reqpc_0a;
        assign ic__rd_req_0a = 1;
        
        assign ic__rd_addr_0a = reqpc_0a;
        assign ic__rd_req_0a = 1;
        

-       

        always @(posedge clk or negedge Nrst)
                if (!Nrst) begin
                        bubble_1a <= 1;
        always @(posedge clk or negedge Nrst)
                if (!Nrst) begin
                        bubble_1a <= 1;

diff --git a/ICache.v b/ICache.v
index 081fc10d3a4732673daff76c707a0ce046ef79dc..dc26fdc4b52f469785d24e844702d3a60453bbeb 100644 (file)
--- a/ICache.v
+++ b/ICache.v
@@ -39,7 +39,7 @@ module ICache(
        
        reg cache_valid [15:0];
        reg [21:0] cache_tags [15:0];
        
        reg cache_valid [15:0];
        reg [21:0] cache_tags [15:0];

-       reg [31:0] cache_data [255:0 /* {line, word} */];       //synthesis attribute ram_style of cache_data is distributed
+       reg [31:0] cache_data [255:0 /* {line, word} */];       //synthesis attribute ram_style of cache_data is block

        
        integer i;
        initial
        
        integer i;
        initial