Fetch.v

   1 module Fetch(
   2         input              clk,
   3         input              Nrst,
   4
   5         output wire [31:0] ic__rd_addr_0a,
   6         output wire        ic__rd_req_0a,
   7         input              ic__rd_wait_0a,
   8         input       [31:0] ic__rd_data_1a,
   9
  10         input              stall_0a,
  11         input              jmp_0a,
  12         input       [31:0] jmppc_0a,
  13         output reg         bubble_1a = 1,
  14         output reg  [31:0] insn_1a = 0,
  15         output reg  [31:0] pc_1a = 32'hFFFFFFFC);
  16
  17         reg qjmp = 0;   /* A jump has been queued up while we were waiting. */
  18         reg [31:0] qjmppc;
  19         always @(posedge clk or negedge Nrst)
  20                 if (!Nrst)
  21                         qjmp <= 0;
  22                 else if ((ic__rd_wait_0a || stall_0a) && jmp_0a)
  23                         {qjmp,qjmppc} <= {jmp_0a, jmppc_0a};
  24                 else if (!ic__rd_wait_0a && !stall_0a && qjmp)  /* It has already been intoed. */
  25                         {qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
  26
  27         reg [31:0] reqpc_0a;
  28
  29         /* Output latch logic */
  30         reg [31:0] insn_2a;
  31         reg stall_1a;
  32         always @(posedge clk or negedge Nrst)
  33                 if (!Nrst) begin
  34                         insn_2a <= 32'h00000000;
  35                         stall_1a <= 0;
  36                 end else begin
  37                         insn_2a <= insn_1a;
  38                         stall_1a <= stall_0a;
  39                 end
  40
  41         always @(*)
  42                 if (stall_1a)
  43                         insn_1a = insn_2a;
  44                 else
  45                         insn_1a = ic__rd_data_1a;
  46
  47         assign ic__rd_addr_0a = reqpc_0a;
  48         assign ic__rd_req_0a = 1;
  49
  50
  51         always @(posedge clk or negedge Nrst)
  52                 if (!Nrst) begin
  53                         bubble_1a <= 1;
  54                         pc_1a <= 32'h00000000;
  55                 end else if (!stall_0a) begin
  56                         bubble_1a <= (jmp_0a || qjmp || ic__rd_wait_0a);
  57                         pc_1a <= reqpc_0a;
  58                 end
  59
  60         always @(posedge clk or negedge Nrst)
  61                 if (!Nrst)
  62                         reqpc_0a <= 0;
  63                 else if (!stall_0a && !ic__rd_wait_0a) begin
  64                         if (qjmp)
  65                                 reqpc_0a <= qjmppc;
  66                         else if (jmp_0a)
  67                                 reqpc_0a <= jmppc_0a;
  68                         else
  69                                 reqpc_0a <= reqpc_0a + 4;
  70                 end
  71 endmodule