DCache, ICache: Move curdata out to its own wire for synthesis. Fix up a blocking...

diff --git a/DCache.v b/DCache.v
index ccaa6b1f5b871429e10d658200556b40ee38937a..f4dff5a41f1b0d8d12b8a3706c0f0d120fa33643 100644 (file)
--- a/DCache.v
+++ b/DCache.v
@@ -48,9 +48,10 @@ module DCache(
        
        wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
        
        
        wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
        

+       wire [31:0] curdata = cache_data[idx][didx_word];

        always @(*) begin
                rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
        always @(*) begin
                rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));

-               rd_data = cache_data[idx][didx_word];
+               rd_data = curdata;

                if (!rw_wait && rd_req)
                        $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data);
        end
                if (!rw_wait && rd_req)
                        $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data);
        end


@@ -90,6 +91,6 @@ module DCache(
                                        cache_valid[idx] <= 0;
                        end
                end else if (wr_req && cache_hit)
                                        cache_valid[idx] <= 0;
                        end
                end else if (wr_req && cache_hit)

-                       cache_data[idx][addr[5:2]] = wr_data;
+                       cache_data[idx][addr[5:2]] <= wr_data;

        end
 endmodule
        end
 endmodule

diff --git a/ICache.v b/ICache.v
index d9fbf04b6f07858a01d965647a989a5231cd3ae3..e6754b722acb93829811c7758d64914ecbc538b2 100644 (file)
--- a/ICache.v
+++ b/ICache.v
@@ -48,10 +48,11 @@ module ICache(
        reg [31:0] prev_rd_addr = 32'hFFFFFFFF;
        
        wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
        reg [31:0] prev_rd_addr = 32'hFFFFFFFF;
        
        wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);

-       
-       always @(*) begin       /* XXX does this work nowadays? */
+
+       wire [31:0] curdata = cache_data[rd_idx][rd_didx_word];
+       always @(*) begin

                rd_wait = rd_req && !cache_hit;
                rd_wait = rd_req && !cache_hit;

-               rd_data = cache_data[rd_idx][rd_didx_word];
+               rd_data = curdata;

        end
        
        reg [3:0] cache_fill_pos = 0;
        end
        
        reg [3:0] cache_fill_pos = 0;