From ac760abbb074404374f0b376981d5b1c695ac9b3 Mon Sep 17 00:00:00 2001 From: Joshua Wise Date: Sat, 24 Jan 2009 03:56:01 -0500 Subject: [PATCH] DCache, ICache: Move curdata out to its own wire for synthesis. Fix up a blocking assign that should be a nonblocking assign. --- DCache.v | 5 +++-- ICache.v | 7 ++++--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/DCache.v b/DCache.v index ccaa6b1..f4dff5a 100644 --- a/DCache.v +++ b/DCache.v @@ -48,9 +48,10 @@ module DCache( wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag); + wire [31:0] curdata = cache_data[idx][didx_word]; always @(*) begin rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready)); - rd_data = cache_data[idx][didx_word]; + rd_data = curdata; if (!rw_wait && rd_req) $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data); end @@ -90,6 +91,6 @@ module DCache( cache_valid[idx] <= 0; end end else if (wr_req && cache_hit) - cache_data[idx][addr[5:2]] = wr_data; + cache_data[idx][addr[5:2]] <= wr_data; end endmodule diff --git a/ICache.v b/ICache.v index d9fbf04..e6754b7 100644 --- a/ICache.v +++ b/ICache.v @@ -48,10 +48,11 @@ module ICache( reg [31:0] prev_rd_addr = 32'hFFFFFFFF; wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag); - - always @(*) begin /* XXX does this work nowadays? */ + + wire [31:0] curdata = cache_data[rd_idx][rd_didx_word]; + always @(*) begin rd_wait = rd_req && !cache_hit; - rd_data = cache_data[rd_idx][rd_didx_word]; + rd_data = curdata; end reg [3:0] cache_fill_pos = 0; -- 2.39.2